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| author | merry <git@mary.rs> | 2022-08-25 11:12:13 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-25 10:12:13 +0000 |
| commit | f5235fff29e797ed76022bbd51e4e64577c83457 (patch) | |
| tree | f5d6be6efd9990cf74bf7272b62942a9438d9814 /ARMeilleure/CodeGen/X86/PreAllocator.cs | |
| parent | eba682b767a60db51ff624ae48a3ca0124634705 (diff) | |
ARMeilleure: Hardware accelerate SHA256 (#3585)
* ARMeilleure/HardwareCapabilities: Add Sha
* ARMeilleure/Intrinsic: Add X86Sha256Rnds2
* ARmeilleure: Hardware accelerate SHA256H/SHA256H2
* ARMeilleure/Intrinsic: Add X86Sha256Msg1, X86Sha256Msg2
* ARMeilleure/Intrinsic: Add X86Palignr
* ARMeilleure: Hardware accelerate SHA256SU0, SHA256SU1
* PTC: Bump InternalVersion
Diffstat (limited to 'ARMeilleure/CodeGen/X86/PreAllocator.cs')
| -rw-r--r-- | ARMeilleure/CodeGen/X86/PreAllocator.cs | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/ARMeilleure/CodeGen/X86/PreAllocator.cs b/ARMeilleure/CodeGen/X86/PreAllocator.cs index 7d2d4df0..dd73a1dd 100644 --- a/ARMeilleure/CodeGen/X86/PreAllocator.cs +++ b/ARMeilleure/CodeGen/X86/PreAllocator.cs @@ -308,11 +308,13 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.Extended: { + bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd || + node.Intrinsic == Intrinsic.X86Blendvps || + node.Intrinsic == Intrinsic.X86Pblendvb; + // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported. - if ((node.Intrinsic == Intrinsic.X86Blendvpd || - node.Intrinsic == Intrinsic.X86Blendvps || - node.Intrinsic == Intrinsic.X86Pblendvb) && - !HardwareCapabilities.SupportsVexEncoding) + // SHA256RNDS2 always has an implied XMM0 as a last operand. + if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2) { Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128); |