diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-12-07 10:37:07 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-07 10:37:07 +0100 |
| commit | 567ea726e173040ae931a37bc85fd6cd92b69363 (patch) | |
| tree | 5b6487d4821c978659732d5f34abf5aa69b0dafa /ARMeilleure/CodeGen/X86/Assembler.cs | |
| parent | 668720b0883106fc1f44da70dddb8a3502ac7dbb (diff) | |
Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)
* Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths).
* Ptc.InternalVersion = 1630
* Nits.
* Address comments.
* Update Ptc.cs
* Address comment.
Diffstat (limited to 'ARMeilleure/CodeGen/X86/Assembler.cs')
| -rw-r--r-- | ARMeilleure/CodeGen/X86/Assembler.cs | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/ARMeilleure/CodeGen/X86/Assembler.cs b/ARMeilleure/CodeGen/X86/Assembler.cs index d65262ea..b9751059 100644 --- a/ARMeilleure/CodeGen/X86/Assembler.cs +++ b/ARMeilleure/CodeGen/X86/Assembler.cs @@ -72,7 +72,7 @@ namespace ARMeilleure.CodeGen.X86 { _instTable = new InstructionInfo[(int)X86Instruction.Count]; - // Name RM/R RM/I8 RM/I32 R/I64 R/RM Flags + // Name RM/R RM/I8 RM/I32 R/I64 R/RM Flags Add(X86Instruction.Add, new InstructionInfo(0x00000001, 0x00000083, 0x00000081, BadOp, 0x00000003, InstructionFlags.None)); Add(X86Instruction.Addpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex | InstructionFlags.Prefix66)); Add(X86Instruction.Addps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex)); @@ -131,6 +131,7 @@ namespace ARMeilleure.CodeGen.X86 Add(X86Instruction.Imul128, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x050000f7, InstructionFlags.None)); Add(X86Instruction.Insertps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a21, InstructionFlags.Vex | InstructionFlags.Prefix66)); Add(X86Instruction.Jmp, new InstructionInfo(0x040000ff, BadOp, BadOp, BadOp, BadOp, InstructionFlags.None)); + Add(X86Instruction.Ldmxcsr, new InstructionInfo(0x02000fae, BadOp, BadOp, BadOp, BadOp, InstructionFlags.Vex)); Add(X86Instruction.Lea, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x0000008d, InstructionFlags.None)); Add(X86Instruction.Maxpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5f, InstructionFlags.Vex | InstructionFlags.Prefix66)); Add(X86Instruction.Maxps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5f, InstructionFlags.Vex)); @@ -257,6 +258,7 @@ namespace ARMeilleure.CodeGen.X86 Add(X86Instruction.Sqrtps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f51, InstructionFlags.Vex)); Add(X86Instruction.Sqrtsd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f51, InstructionFlags.Vex | InstructionFlags.PrefixF2)); Add(X86Instruction.Sqrtss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f51, InstructionFlags.Vex | InstructionFlags.PrefixF3)); + Add(X86Instruction.Stmxcsr, new InstructionInfo(0x03000fae, BadOp, BadOp, BadOp, BadOp, InstructionFlags.Vex)); Add(X86Instruction.Sub, new InstructionInfo(0x00000029, 0x05000083, 0x05000081, BadOp, 0x0000002b, InstructionFlags.None)); Add(X86Instruction.Subpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5c, InstructionFlags.Vex | InstructionFlags.Prefix66)); Add(X86Instruction.Subps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5c, InstructionFlags.Vex)); @@ -526,6 +528,11 @@ namespace ARMeilleure.CodeGen.X86 WriteInstruction(dest, null, OperandType.None, X86Instruction.Jmp); } + public void Ldmxcsr(Operand dest) + { + WriteInstruction(dest, null, OperandType.I32, X86Instruction.Ldmxcsr); + } + public void Lea(Operand dest, Operand source, OperandType type) { WriteInstruction(dest, source, type, X86Instruction.Lea); @@ -796,6 +803,11 @@ namespace ARMeilleure.CodeGen.X86 WriteOpCode(dest, null, null, OperandType.None, info.Flags, info.OpRRM | (int)condition); } + public void Stmxcsr(Operand dest) + { + WriteInstruction(dest, null, OperandType.I32, X86Instruction.Stmxcsr); + } + public void Sub(Operand dest, Operand source, OperandType type) { WriteInstruction(dest, source, type, X86Instruction.Sub); |