aboutsummaryrefslogtreecommitdiff
path: root/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
diff options
context:
space:
mode:
authorFICTURE7 <FICTURE7@gmail.com>2021-08-17 22:08:34 +0400
committerGitHub <noreply@github.com>2021-08-17 15:08:34 -0300
commit22b2cb39af00fb8881e908fd671fbf57a6e2db2a (patch)
treea79e2df801d7f16a33ff50b3c5bfed303cb476e9 /ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
parentcd4530f29c6a4ffd1b023105350b0440fa63f47b (diff)
Reduce JIT GC allocations (#2515)
* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
Diffstat (limited to 'ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs')
-rw-r--r--ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs244
1 files changed, 129 insertions, 115 deletions
diff --git a/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs b/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
index 2f68c43f..7b339efb 100644
--- a/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
+++ b/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
@@ -1,11 +1,10 @@
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
-using System.Collections.Generic;
+using System;
using System.Diagnostics;
using System.Numerics;
-
-using static ARMeilleure.IntermediateRepresentation.OperandHelper;
-using static ARMeilleure.IntermediateRepresentation.OperationHelper;
+using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
+using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
@@ -29,19 +28,14 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
}
}
- private class LocalInfo
+ private struct LocalInfo
{
- public int Uses { get; set; }
- public int UseCount { get; set; }
-
- public bool PreAllocated { get; set; }
- public int Register { get; set; }
- public int SpillOffset { get; set; }
-
+ public int Uses { get; set; }
+ public int UsesAllocated { get; set; }
+ public int Register { get; set; }
+ public int SpillOffset { get; set; }
public int Sequence { get; set; }
-
public Operand Temp { get; set; }
-
public OperandType Type { get; }
private int _first;
@@ -49,13 +43,21 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
public bool IsBlockLocal => _first == _last;
- public LocalInfo(OperandType type, int uses)
+ public LocalInfo(OperandType type, int uses, int blkIndex)
{
Uses = uses;
Type = type;
+ UsesAllocated = 0;
+ Register = 0;
+ SpillOffset = 0;
+ Sequence = 0;
+ Temp = default;
+
_first = -1;
_last = -1;
+
+ SetBlockIndex(blkIndex);
}
public void SetBlockIndex(int blkIndex)
@@ -72,10 +74,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
}
}
- public AllocationResult RunPass(
- ControlFlowGraph cfg,
- StackAllocator stackAlloc,
- RegisterMasks regMasks)
+ public AllocationResult RunPass(ControlFlowGraph cfg, StackAllocator stackAlloc, RegisterMasks regMasks)
{
int intUsedRegisters = 0;
int vecUsedRegisters = 0;
@@ -84,9 +83,33 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
int vecFreeRegisters = regMasks.VecAvailableRegisters;
var blockInfo = new BlockInfo[cfg.Blocks.Count];
+ var localInfo = new LocalInfo[cfg.Blocks.Count * 3];
+ int localInfoCount = 0;
+
+ // The "visited" state is stored in the MSB of the local's value.
+ const ulong VisitedMask = 1ul << 63;
+
+ bool IsVisited(Operand local)
+ {
+ return (local.GetValueUnsafe() & VisitedMask) != 0;
+ }
+
+ void SetVisited(Operand local)
+ {
+ local.GetValueUnsafe() |= VisitedMask | (uint)++localInfoCount;
+ }
+
+ ref LocalInfo GetLocalInfo(Operand local)
+ {
+ Debug.Assert(local.Kind == OperandKind.LocalVariable);
+
+ if (!IsVisited(local))
+ {
+ throw new InvalidOperationException("Local was not visisted yet. Used before defined?");
+ }
- var locInfo = new List<LocalInfo>();
- var locVisited = new HashSet<Operand>();
+ return ref localInfo[(uint)local.GetValueUnsafe() - 1];
+ }
for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
{
@@ -97,59 +120,58 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
bool hasCall = false;
- for (Node node = block.Operations.First; node != null; node = node.ListNext)
+ for (Operation node = block.Operations.First; node != default; node = node.ListNext)
{
- if (node is Operation operation && operation.Instruction == Instruction.Call)
+ if (node.Instruction == Instruction.Call)
{
hasCall = true;
}
- for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
+ for (int i = 0; i < node.SourcesCount; i++)
{
- Operand source = node.GetSource(srcIndex);
+ Operand source = node.GetSource(i);
if (source.Kind == OperandKind.LocalVariable)
{
- locInfo[source.GetLocalNumber() - 1].SetBlockIndex(block.Index);
+ GetLocalInfo(source).SetBlockIndex(block.Index);
}
else if (source.Kind == OperandKind.Memory)
{
- MemoryOperand memOp = (MemoryOperand)source;
+ MemoryOperand memOp = source.GetMemory();
- if (memOp.BaseAddress != null)
+ if (memOp.BaseAddress != default)
{
- locInfo[memOp.BaseAddress.GetLocalNumber() - 1].SetBlockIndex(block.Index);
+ GetLocalInfo(memOp.BaseAddress).SetBlockIndex(block.Index);
}
- if (memOp.Index != null)
+ if (memOp.Index != default)
{
- locInfo[memOp.Index.GetLocalNumber() - 1].SetBlockIndex(block.Index);
+ GetLocalInfo(memOp.Index).SetBlockIndex(block.Index);
}
}
}
- for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
+ for (int i = 0; i < node.DestinationsCount; i++)
{
- Operand dest = node.GetDestination(dstIndex);
+ Operand dest = node.GetDestination(i);
if (dest.Kind == OperandKind.LocalVariable)
{
- LocalInfo info;
-
- if (!locVisited.Add(dest))
+ if (IsVisited(dest))
{
- info = locInfo[dest.GetLocalNumber() - 1];
+ GetLocalInfo(dest).SetBlockIndex(block.Index);
}
else
{
- dest.NumberLocal(locInfo.Count + 1);
+ SetVisited(dest);
- info = new LocalInfo(dest.Type, UsesCount(dest));
+ if (localInfoCount > localInfo.Length)
+ {
+ Array.Resize(ref localInfo, localInfoCount * 2);
+ }
- locInfo.Add(info);
+ GetLocalInfo(dest) = new LocalInfo(dest.Type, UsesCount(dest), block.Index);
}
-
- info.SetBlockIndex(block.Index);
}
else if (dest.Kind == OperandKind.Register)
{
@@ -192,42 +214,26 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
intLocalFreeRegisters &= ~(intSpillTempRegisters | intCallerSavedRegisters);
vecLocalFreeRegisters &= ~(vecSpillTempRegisters | vecCallerSavedRegisters);
- for (Node node = block.Operations.First; node != null; node = node.ListNext)
+ for (Operation node = block.Operations.First; node != default; node = node.ListNext)
{
int intLocalUse = 0;
int vecLocalUse = 0;
- void AllocateRegister(Operand source, MemoryOperand memOp, int srcIndex)
+ Operand AllocateRegister(Operand local)
{
- LocalInfo info = locInfo[source.GetLocalNumber() - 1];
+ ref LocalInfo info = ref GetLocalInfo(local);
- info.UseCount++;
+ info.UsesAllocated++;
- Debug.Assert(info.UseCount <= info.Uses);
+ Debug.Assert(info.UsesAllocated <= info.Uses);
if (info.Register != -1)
{
- Operand reg = Register(info.Register, source.Type.ToRegisterType(), source.Type);
-
- if (memOp != null)
- {
- if (srcIndex == 0)
- {
- memOp.BaseAddress = reg;
- }
- else /* if (srcIndex == 1) */
- {
- memOp.Index = reg;
- }
- }
- else
- {
- node.SetSource(srcIndex, reg);
- }
+ Operand reg = Register(info.Register, local.Type.ToRegisterType(), local.Type);
- if (info.UseCount == info.Uses && !info.PreAllocated)
+ if (info.UsesAllocated == info.Uses)
{
- if (source.Type.IsInteger())
+ if (local.Type.IsInteger())
{
intLocalFreeRegisters |= 1 << info.Register;
}
@@ -236,72 +242,80 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
vecLocalFreeRegisters |= 1 << info.Register;
}
}
- }
- else if (node is Operation operation && operation.Instruction == Instruction.Copy)
- {
- Operation fillOp = Operation(Instruction.Fill, node.Destination, Const(info.SpillOffset));
- block.Operations.AddBefore(node, fillOp);
- block.Operations.Remove(node);
-
- node = fillOp;
+ return reg;
}
else
{
Operand temp = info.Temp;
- if (temp == null || info.Sequence != sequence)
+ if (temp == default || info.Sequence != sequence)
{
- temp = source.Type.IsInteger()
- ? GetSpillTemp(source, intSpillTempRegisters, ref intLocalUse)
- : GetSpillTemp(source, vecSpillTempRegisters, ref vecLocalUse);
+ temp = local.Type.IsInteger()
+ ? GetSpillTemp(local, intSpillTempRegisters, ref intLocalUse)
+ : GetSpillTemp(local, vecSpillTempRegisters, ref vecLocalUse);
info.Sequence = sequence;
info.Temp = temp;
}
- if (memOp != null)
- {
- if (srcIndex == 0)
- {
- memOp.BaseAddress = temp;
- }
- else /* if (srcIndex == 1) */
- {
- memOp.Index = temp;
- }
- }
- else
- {
- node.SetSource(srcIndex, temp);
- }
-
Operation fillOp = Operation(Instruction.Fill, temp, Const(info.SpillOffset));
block.Operations.AddBefore(node, fillOp);
+
+ return temp;
}
}
- for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
+ bool folded = false;
+
+ // If operation is a copy of a local and that local is living on the stack, we turn the copy into
+ // a fill, instead of inserting a fill before it.
+ if (node.Instruction == Instruction.Copy)
{
- Operand source = node.GetSource(srcIndex);
+ Operand source = node.GetSource(0);
if (source.Kind == OperandKind.LocalVariable)
{
- AllocateRegister(source, null, srcIndex);
+ ref LocalInfo info = ref GetLocalInfo(source);
+
+ if (info.Register == -1)
+ {
+ Operation fillOp = Operation(Instruction.Fill, node.Destination, Const(info.SpillOffset));
+
+ block.Operations.AddBefore(node, fillOp);
+ block.Operations.Remove(node);
+
+ node = fillOp;
+
+ folded = true;
+ }
}
- else if (source.Kind == OperandKind.Memory)
+ }
+
+ if (!folded)
+ {
+ for (int i = 0; i < node.SourcesCount; i++)
{
- MemoryOperand memOp = (MemoryOperand)source;
+ Operand source = node.GetSource(i);
- if (memOp.BaseAddress != null)
+ if (source.Kind == OperandKind.LocalVariable)
{
- AllocateRegister(memOp.BaseAddress, memOp, 0);
+ node.SetSource(i, AllocateRegister(source));
}
-
- if (memOp.Index != null)
+ else if (source.Kind == OperandKind.Memory)
{
- AllocateRegister(memOp.Index, memOp, 1);
+ MemoryOperand memOp = source.GetMemory();
+
+ if (memOp.BaseAddress != default)
+ {
+ memOp.BaseAddress = AllocateRegister(memOp.BaseAddress);
+ }
+
+ if (memOp.Index != default)
+ {
+ memOp.Index = AllocateRegister(memOp.Index);
+ }
}
}
}
@@ -309,18 +323,18 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
int intLocalAsg = 0;
int vecLocalAsg = 0;
- for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
+ for (int i = 0; i < node.DestinationsCount; i++)
{
- Operand dest = node.GetDestination(dstIndex);
+ Operand dest = node.GetDestination(i);
if (dest.Kind != OperandKind.LocalVariable)
{
continue;
}
- LocalInfo info = locInfo[dest.GetLocalNumber() - 1];
+ ref LocalInfo info = ref GetLocalInfo(dest);
- if (info.UseCount == 0 && !info.PreAllocated)
+ if (info.UsesAllocated == 0)
{
int mask = dest.Type.IsInteger()
? intLocalFreeRegisters
@@ -350,19 +364,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
}
}
- info.UseCount++;
+ info.UsesAllocated++;
- Debug.Assert(info.UseCount <= info.Uses);
+ Debug.Assert(info.UsesAllocated <= info.Uses);
if (info.Register != -1)
{
- node.SetDestination(dstIndex, Register(info.Register, dest.Type.ToRegisterType(), dest.Type));
+ node.SetDestination(i, Register(info.Register, dest.Type.ToRegisterType(), dest.Type));
}
else
{
Operand temp = info.Temp;
- if (temp == null || info.Sequence != sequence)
+ if (temp == default || info.Sequence != sequence)
{
temp = dest.Type.IsInteger()
? GetSpillTemp(dest, intSpillTempRegisters, ref intLocalAsg)
@@ -372,9 +386,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
info.Temp = temp;
}
- node.SetDestination(dstIndex, temp);
+ node.SetDestination(i, temp);
- Operation spillOp = Operation(Instruction.Spill, null, Const(info.SpillOffset), temp);
+ Operation spillOp = Operation(Instruction.Spill, default, Const(info.SpillOffset), temp);
block.Operations.AddAfter(node, spillOp);
@@ -435,7 +449,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
private static int UsesCount(Operand local)
{
- return local.Assignments.Count + local.Uses.Count;
+ return local.AssignmentsCount + local.UsesCount;
}
}
} \ No newline at end of file