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authorMichael Gielda <mgielda@antmicro.com>2021-09-15 01:47:10 +0200
committerGitHub <noreply@github.com>2021-09-15 01:47:10 +0200
commitfb2e61a435f6a9d2201d521df47c9bfd12031df3 (patch)
treeb31f1d5b1d262ce9bfae673afc621dc34a402178
parent5d08e9b495a2315e8a4758a8123466665085d044 (diff)
Add Linux Unicorn patch + desc. (#2609)
-rw-r--r--Ryujinx.Tests.Unicorn/libs/README.md23
-rw-r--r--Ryujinx.Tests.Unicorn/libs/linux/unicorn_fspcr.patch24
2 files changed, 45 insertions, 2 deletions
diff --git a/Ryujinx.Tests.Unicorn/libs/README.md b/Ryujinx.Tests.Unicorn/libs/README.md
index bb370164..427044f9 100644
--- a/Ryujinx.Tests.Unicorn/libs/README.md
+++ b/Ryujinx.Tests.Unicorn/libs/README.md
@@ -1,3 +1,22 @@
-The pre-compiled dynamic libraries in this directory are licenced under the GPLv2.
+# Unicorn
-The source code for windows/unicorn.dll is available at: https://github.com/MerryMage/UnicornDotNet/tree/299451c02d9c810d2feca51f5e9cb6d8b2f38960
+Unicorn is a CPU simulator with bindings in many languages, including
+C#/.NET.
+It is used by the Ryujinx test suite for comparative testing with its built-in
+CPU simulator, Armeilleure.
+
+## Windows
+
+On Windows, Unicorn is shipped as a pre-compiled dynamic library (`.dll`), licenced under the GPLv2.
+
+The source code for `windows/unicorn.dll` is available at: https://github.com/MerryMage/UnicornDotNet/tree/299451c02d9c810d2feca51f5e9cb6d8b2f38960
+
+## Linux
+
+On Linux, you will first need to download Unicorn from https://github.com/unicorn-engine/unicorn.
+
+Then you need to patch it to expose the FSPCR register by applying `linux/unicorn_fspcr.patch`
+
+Then, compile Unicorn from source with its `make.sh` script.
+
+See https://github.com/Ryujinx/Ryujinx/pull/1433 for details.
diff --git a/Ryujinx.Tests.Unicorn/libs/linux/unicorn_fspcr.patch b/Ryujinx.Tests.Unicorn/libs/linux/unicorn_fspcr.patch
new file mode 100644
index 00000000..391c2fb6
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/libs/linux/unicorn_fspcr.patch
@@ -0,0 +1,24 @@
+diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c
+index 5ff9ebb..d4953f4 100644
+--- a/qemu/target-arm/unicorn_arm.c
++++ b/qemu/target-arm/unicorn_arm.c
+@@ -101,6 +101,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
+ case UC_ARM_REG_FPEXC:
+ *(int32_t *)value = ARM_CPU(uc, mycpu)->env.vfp.xregs[ARM_VFP_FPEXC];
+ break;
++ case UC_ARM_REG_FPSCR:
++ *(int32_t *)value = vfp_get_fpscr(&ARM_CPU(uc, mycpu)->env);
++ break;
+ case UC_ARM_REG_IPSR:
+ *(uint32_t *)value = xpsr_read(&ARM_CPU(uc, mycpu)->env) & 0x1ff;
+ break;
+@@ -175,6 +178,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
+ case UC_ARM_REG_FPEXC:
+ ARM_CPU(uc, mycpu)->env.vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value;
+ break;
++ case UC_ARM_REG_FPSCR:
++ vfp_set_fpscr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
++ break;
+ case UC_ARM_REG_IPSR:
+ xpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, 0x1ff);
+ break;