diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2021-12-19 11:19:05 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-19 11:19:05 -0300 |
| commit | e24949ca2c7051586f6518ef524c93db0d4827c2 (patch) | |
| tree | 63665e40395208d922532047415332b0284f53bd | |
| parent | 267b248c1397b50ba874a592303ad250d630eacd (diff) | |
Implement CSDB instruction (#2927)
| -rw-r--r-- | ARMeilleure/Decoders/OpCodeTable.cs | 1 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitMemoryEx32.cs | 5 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdMemory32.cs | 10 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstName.cs | 1 |
4 files changed, 12 insertions, 5 deletions
diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs index 9eb92523..17c83e03 100644 --- a/ARMeilleure/Decoders/OpCodeTable.cs +++ b/ARMeilleure/Decoders/OpCodeTable.cs @@ -661,6 +661,7 @@ namespace ARMeilleure.Decoders SetA32("<<<<00010100xxxxxxxx00100100xxxx", InstName.Crc32cw, InstEmit32.Crc32cw, OpCode32AluReg.Create); SetA32("<<<<00010010xxxxxxxx00000100xxxx", InstName.Crc32h, InstEmit32.Crc32h, OpCode32AluReg.Create); SetA32("<<<<00010100xxxxxxxx00000100xxxx", InstName.Crc32w, InstEmit32.Crc32w, OpCode32AluReg.Create); + SetA32("<<<<0011001000001111000000010100", InstName.Csdb, InstEmit32.Csdb, OpCode32.Create); SetA32("1111010101111111111100000101xxxx", InstName.Dmb, InstEmit32.Dmb, OpCode32.Create); SetA32("1111010101111111111100000100xxxx", InstName.Dsb, InstEmit32.Dsb, OpCode32.Create); SetA32("<<<<0010001xxxxxxxxxxxxxxxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCode32AluImm.Create); diff --git a/ARMeilleure/Instructions/InstEmitMemoryEx32.cs b/ARMeilleure/Instructions/InstEmitMemoryEx32.cs index 28fe000d..9a9787cf 100644 --- a/ARMeilleure/Instructions/InstEmitMemoryEx32.cs +++ b/ARMeilleure/Instructions/InstEmitMemoryEx32.cs @@ -16,6 +16,11 @@ namespace ARMeilleure.Instructions EmitClearExclusive(context); } + public static void Csdb(ArmEmitterContext context) + { + // Execute as no-op. + } + public static void Dmb(ArmEmitterContext context) => EmitBarrier(context); public static void Dsb(ArmEmitterContext context) => EmitBarrier(context); diff --git a/ARMeilleure/Instructions/InstEmitSimdMemory32.cs b/ARMeilleure/Instructions/InstEmitSimdMemory32.cs index 1e8f7ccd..72474ee3 100644 --- a/ARMeilleure/Instructions/InstEmitSimdMemory32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdMemory32.cs @@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions EmitLoadSimd(context, address, GetVecA32(dreg >> 1), dreg >> 1, rIndex++, op.Size); } } - } + } else { EmitLoadSimd(context, address, GetVecA32(d >> 1), d >> 1, index, op.Size); @@ -120,13 +120,13 @@ namespace ARMeilleure.Instructions { Operand m = GetIntA32(context, op.Rm); SetIntA32(context, op.Rn, context.Add(n, m)); - } + } else { SetIntA32(context, op.Rn, context.Add(n, Const(count * eBytes))); } } - } + } else { OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp; @@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions } else { - + if (load) { EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size); @@ -213,7 +213,7 @@ namespace ARMeilleure.Instructions int sReg = (op.DoubleWidth) ? (op.Vd << 1) : op.Vd; int offset = 0; int byteSize = 4; - + for (int num = 0; num < range; num++, sReg++) { Operand address = context.Add(baseAddress, Const(offset)); diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs index ce1c53cc..a9c443f1 100644 --- a/ARMeilleure/Instructions/InstName.cs +++ b/ARMeilleure/Instructions/InstName.cs @@ -36,6 +36,7 @@ namespace ARMeilleure.Instructions Crc32ch, Crc32cw, Crc32cx, + Csdb, Csel, Csinc, Csinv, |