Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

3 files changed, 168 insertions, 12 deletions

diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 8b6e234c..14dbf1d6 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -213,15 +213,15 @@ namespace ChocolArm64.Instruction
             }
         }
 
-        private static void EmitQxtn(AILEmitterCtx Context, bool Signed, bool Scalar)
+        private static void EmitSaturatingExtNarrow(AILEmitterCtx Context, bool SignedSrc, bool SignedDst, bool Scalar)
         {
             AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
 
             int Elems = (!Scalar ? 8 >> Op.Size : 1);
             int ESize = 8 << Op.Size;
 
-            int TMaxValue = (Signed ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
-            int TMinValue = (Signed ? -((1 << (ESize - 1))) : 0);
+            int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
+            int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
 
             int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
 
@@ -233,14 +233,14 @@ namespace ChocolArm64.Instruction
                 AILLabel LblLe    = new AILLabel();
                 AILLabel LblGeEnd = new AILLabel();
 
-                EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
+                EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
 
                 Context.Emit(OpCodes.Dup);
 
                 Context.EmitLdc_I4(TMaxValue);
                 Context.Emit(OpCodes.Conv_U8);
 
-                Context.Emit(Signed ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
+                Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
 
                 Context.Emit(OpCodes.Pop);
 
@@ -258,7 +258,7 @@ namespace ChocolArm64.Instruction
                 Context.EmitLdc_I4(TMinValue);
                 Context.Emit(OpCodes.Conv_I8);
 
-                Context.Emit(Signed ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
+                Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
 
                 Context.Emit(OpCodes.Pop);
 
@@ -1137,22 +1137,22 @@ namespace ChocolArm64.Instruction
 
         public static void Sqxtn_S(AILEmitterCtx Context)
         {
-            EmitQxtn(Context, Signed: true, Scalar: true);
+            EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: true);
         }
 
         public static void Sqxtn_V(AILEmitterCtx Context)
         {
-            EmitQxtn(Context, Signed: true, Scalar: false);
+            EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: false);
         }
 
         public static void Sqxtun_S(AILEmitterCtx Context)
         {
-            EmitQxtn(Context, Signed: false, Scalar: true);
+            EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: true);
         }
 
         public static void Sqxtun_V(AILEmitterCtx Context)
         {
-            EmitQxtn(Context, Signed: false, Scalar: false);
+            EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: false);
         }
 
         public static void Sub_S(AILEmitterCtx Context)
@@ -1243,12 +1243,12 @@ namespace ChocolArm64.Instruction
 
         public static void Uqxtn_S(AILEmitterCtx Context)
         {
-            EmitQxtn(Context, Signed: false, Scalar: true);
+            EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: true);
         }
 
         public static void Uqxtn_V(AILEmitterCtx Context)
         {
-            EmitQxtn(Context, Signed: false, Scalar: false);
+            EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: false);
         }
     }
 }
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 90461728..100f6e0a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -851,6 +851,82 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
         }
 
+        [Test, Description("SQXTUN <Vb><d>, <Va><n>")]
+        public void Sqxtun_S_HB_SH_DS([ValueSource("_1H1S1D_")] [Random(1)] ulong A,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
+        {
+            uint Opcode = 0x7E212820; // SQXTUN B0, H1
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
+                                                 TestContext.CurrentContext.Random.NextULong());
+            Vector128<float> V1 = MakeVectorE0(A);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
+
+            AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong()));
+            AArch64.V(1, new Bits(A));
+            SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
+            });
+            Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
+        }
+
+        [Test, Pairwise, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
+        public void Sqxtun_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
+                                            [ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
+                                            [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S>
+        {
+            uint Opcode = 0x2E212820; // SQXTUN V0.8B, V1.8H
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
+            Vector128<float> V1 = MakeVectorE0E1(A0, A1);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
+
+            AArch64.Vpart(1, 0, new Bits(A0));
+            AArch64.Vpart(1, 1, new Bits(A1));
+            SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
+            });
+            Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
+        }
+
+        [Test, Pairwise, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
+        public void Sqxtun_V_8H16B_4S8H_2D4S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
+                                             [ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
+                                             [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S>
+        {
+            uint Opcode = 0x6E212820; // SQXTUN2 V0.16B, V1.8H
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            ulong _X0 = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> V0 = MakeVectorE0(_X0);
+            Vector128<float> V1 = MakeVectorE0E1(A0, A1);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
+
+            AArch64.Vpart(1, 0, new Bits(A0));
+            AArch64.Vpart(1, 1, new Bits(A1));
+            SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+            Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
+        }
+
         [Test, Description("UQXTN <Vb><d>, <Va><n>")]
         public void Uqxtn_S_HB_SH_DS([ValueSource("_1H1S1D_")] [Random(1)] ulong A,
                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs
index a4e04e96..5738f599 100644
--- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs
+++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs
@@ -2889,6 +2889,86 @@ namespace Ryujinx.Tests.Cpu.Tester
             Vpart(d, part, result);
         }
 
+        // sqxtun_advsimd.html#SQXTUN_asisdmisc_N
+        public static void Sqxtun_S(Bits size, Bits Rn, Bits Rd)
+        {
+            /* Decode Scalar */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = esize;
+            int part = 0;
+            int elements = 1;
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand = V(2 * datasize, n);
+            Bits element;
+            bool sat;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element = Elem(operand, e, 2 * esize);
+
+                (Bits _result, bool _sat) = UnsignedSatQ(SInt(element), esize);
+                Elem(result, e, esize, _result);
+                sat = _sat;
+
+                if (sat)
+                {
+                    /* FPSR.QC = '1'; */
+                    FPSR[27] = true; // TODO: Add named fields.
+                }
+            }
+
+            Vpart(d, part, result);
+        }
+
+        // sqxtun_advsimd.html#SQXTUN_asimdmisc_N
+        public static void Sqxtun_V(bool Q, Bits size, Bits Rn, Bits Rd)
+        {
+            /* Decode Vector */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand = V(2 * datasize, n);
+            Bits element;
+            bool sat;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element = Elem(operand, e, 2 * esize);
+
+                (Bits _result, bool _sat) = UnsignedSatQ(SInt(element), esize);
+                Elem(result, e, esize, _result);
+                sat = _sat;
+
+                if (sat)
+                {
+                    /* FPSR.QC = '1'; */
+                    FPSR[27] = true; // TODO: Add named fields.
+                }
+            }
+
+            Vpart(d, part, result);
+        }
+
         // uqxtn_advsimd.html#UQXTN_asisdmisc_N
         public static void Uqxtn_S(Bits size, Bits Rn, Bits Rd)
         {