diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-15 22:36:47 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-15 22:36:47 -0300 |
| commit | 88c6160c62b000d155a829b23e6207d78b7dccfa (patch) | |
| tree | a386af75b5c61a137bca7de578d9b6505002f0b2 | |
| parent | 79a59397349b40758fc75cd2e19c67726a77e975 (diff) | |
Add MLA (vector by element), fixes some cases of MUL (vector by element)?
| -rw-r--r-- | ChocolArm64/AOpCodeTable.cs | 1 | ||||
| -rw-r--r-- | ChocolArm64/Decoder/AOpCodeSimdRegElem.cs | 5 | ||||
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | 9 | ||||
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 7 |
4 files changed, 17 insertions, 5 deletions
diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index d32bd9cd..9240c0a7 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -228,6 +228,7 @@ namespace ChocolArm64 Set("xx111100x11xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemReg)); Set("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeSimdMemLit)); Set("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg)); + Set("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem)); Set("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg)); Set("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); Set("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs index 721da88f..d6dc4bd2 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs +++ b/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs @@ -11,9 +11,8 @@ namespace ChocolArm64.Decoder switch (Size) { case 1: - Index = (OpCode >> 21) & 1 | - (OpCode >> 10) & 2 | - (OpCode >> 18) & 4; + Index = (OpCode >> 20) & 3 | + (OpCode >> 9) & 4; Rm &= 0xf; diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs index bf980a58..989b470e 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs @@ -335,6 +335,15 @@ namespace ChocolArm64.Instruction }); } + public static void Mla_Ve(AILEmitterCtx Context) + { + EmitVectorTernaryOpByElemZx(Context, () => + { + Context.Emit(OpCodes.Mul); + Context.Emit(OpCodes.Add); + }); + } + public static void Mls_V(AILEmitterCtx Context) { EmitVectorTernaryOpZx(Context, () => diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index 4e45a11d..d8642e99 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -381,13 +381,16 @@ namespace ChocolArm64.Instruction } EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed); - EmitVectorExtract(Context, Op.Rm, Index, Op.Size, Signed); + EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed); Emit(); - EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + EmitVectorInsertTmp(Context, Index, Op.Size); } + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); |