diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-02 20:03:28 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-02 20:03:28 -0300 |
| commit | 829b1b1cc0a7dced1946500c1f27b4a7277ddb26 (patch) | |
| tree | 7e2a63127147ff1e2031be3d9ec45628229b8a27 | |
| parent | f39a864050589ac7e757a9d72b46ac693125b382 (diff) | |
Add REV64 (vector) instruction
| -rw-r--r-- | ChocolArm64/AOpCodeTable.cs | 1 | ||||
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdLogical.cs | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 470b70e0..13df4d98 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -230,6 +230,7 @@ namespace ChocolArm64 Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd)); Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg)); Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm)); + Set("0x001110xx100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd)); Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg)); Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt)); Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs index ea4b17b3..f4cc66cf 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs @@ -1,4 +1,5 @@ using ChocolArm64.Translation; +using System; using System.Reflection.Emit; using static ChocolArm64.Instruction.AInstEmitSimdHelper; @@ -65,5 +66,15 @@ namespace ChocolArm64.Instruction { EmitVectorImmBinaryOp(Context, () => Context.Emit(OpCodes.Or)); } + + public static void Rev64_V(AILEmitterCtx Context) + { + Action Emit = () => + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64)); + }; + + EmitVectorUnaryOpZx(Context, Emit); + } } }
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