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authormerry <git@mary.rs>2022-08-14 21:35:08 +0100
committerGitHub <noreply@github.com>2022-08-14 17:35:08 -0300
commit6dfb6ccf8cac7d50d08bec08198686032d7e6630 (patch)
tree3b8331634f7da6555ab64ac38ce3a42aeb71bf87
parente87e8b012c1fdfdbfbfe374506a28fe3155cfce2 (diff)
PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandDestSrc1 (#3587)
-rw-r--r--ARMeilleure/CodeGen/X86/AssemblerTable.cs5
-rw-r--r--ARMeilleure/CodeGen/X86/PreAllocator.cs6
2 files changed, 10 insertions, 1 deletions
diff --git a/ARMeilleure/CodeGen/X86/AssemblerTable.cs b/ARMeilleure/CodeGen/X86/AssemblerTable.cs
index 68791fbb..3af42204 100644
--- a/ARMeilleure/CodeGen/X86/AssemblerTable.cs
+++ b/ARMeilleure/CodeGen/X86/AssemblerTable.cs
@@ -4,6 +4,11 @@ namespace ARMeilleure.CodeGen.X86
{
partial class Assembler
{
+ public static bool SupportsVexPrefix(X86Instruction inst)
+ {
+ return _instTable[(int)inst].Flags.HasFlag(InstructionFlags.Vex);
+ }
+
private const int BadOp = 0;
[Flags]
diff --git a/ARMeilleure/CodeGen/X86/PreAllocator.cs b/ARMeilleure/CodeGen/X86/PreAllocator.cs
index 72bf64ed..7d2d4df0 100644
--- a/ARMeilleure/CodeGen/X86/PreAllocator.cs
+++ b/ARMeilleure/CodeGen/X86/PreAllocator.cs
@@ -1297,11 +1297,15 @@ namespace ARMeilleure.CodeGen.X86
{
if (IsIntrinsic(operation.Instruction))
{
+ IntrinsicInfo info = IntrinsicTable.GetInfo(operation.Intrinsic);
+
+ bool hasVex = HardwareCapabilities.SupportsVexEncoding && Assembler.SupportsVexPrefix(info.Inst);
+
bool isUnary = operation.SourcesCount < 2;
bool hasVecDest = operation.Destination != default && operation.Destination.Type == OperandType.V128;
- return !HardwareCapabilities.SupportsVexEncoding && !isUnary && hasVecDest;
+ return !hasVex && !isUnary && hasVecDest;
}
return false;