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authorgdkchan <gab.dark.100@gmail.com>2018-03-30 23:32:06 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-30 23:32:06 -0300
commit0ac4681fa06cac24b14bff45f334f453baf74934 (patch)
tree49933236c52c8ece8857b6b3477789c7b6d33483
parent53e2d34905c9e5d03f47ea9a5f9f978b5c4925f6 (diff)
Fix 32-bits extended register instructions with 64-bits extensions
-rw-r--r--ChocolArm64/Translation/AILEmitterCtx.cs16
1 files changed, 11 insertions, 5 deletions
diff --git a/ChocolArm64/Translation/AILEmitterCtx.cs b/ChocolArm64/Translation/AILEmitterCtx.cs
index 46659469..03b06610 100644
--- a/ChocolArm64/Translation/AILEmitterCtx.cs
+++ b/ChocolArm64/Translation/AILEmitterCtx.cs
@@ -72,7 +72,7 @@ namespace ChocolArm64.Translation
Emitter = new AILEmitter(Graph, Root, SubName);
- ILBlock = Emitter.GetILBlock(0);
+ ILBlock = Emitter.GetILBlock(0);
OpcIndex = -1;
@@ -260,18 +260,24 @@ namespace ChocolArm64.Translation
case AIntType.Int64: Emit(OpCodes.Conv_I8); break;
}
- if (IntType == AIntType.UInt64 ||
- IntType == AIntType.Int64)
+ bool Sz64 = CurrOp.RegisterSize != ARegisterSize.Int32;
+
+ if (Sz64 == (IntType == AIntType.UInt64 ||
+ IntType == AIntType.Int64))
{
return;
}
- if (CurrOp.RegisterSize != ARegisterSize.Int32)
+ if (Sz64)
{
Emit(IntType >= AIntType.Int8
? OpCodes.Conv_I8
: OpCodes.Conv_U8);
}
+ else
+ {
+ Emit(OpCodes.Conv_U4);
+ }
}
public void EmitLsl(int Amount) => EmitILShift(Amount, OpCodes.Shl);
@@ -298,7 +304,7 @@ namespace ChocolArm64.Translation
EmitLdc_I4(Amount);
Emit(OpCodes.Shr_Un);
-
+
Ldloc(Tmp2Index, AIoType.Int);
EmitLdc_I4(CurrOp.GetBitsCount() - Amount);