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| author | gdkchan <gab.dark.100@gmail.com> | 2018-07-09 22:48:28 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-09 22:48:28 -0300 |
| commit | 0a36bfbf921038e8eb7d4294ec8543903c933d90 (patch) | |
| tree | 0a92b6ff024d84448f08564ceb1c416cb02cb7fe | |
| parent | 095db47e132a475e25d128e691ebdae101611cc9 (diff) | |
Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm (#239)
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdMove.cs | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs index 95fe5949..d67946a9 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs @@ -339,9 +339,12 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size); - EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + EmitVectorInsertTmp(Context, Index, Op.Size); } + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); @@ -363,9 +366,12 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem, Op.Size); - EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + EmitVectorInsertTmp(Context, Index, Op.Size); } + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); @@ -387,9 +393,12 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size); - EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + EmitVectorInsertTmp(Context, Index, Op.Size); } + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); |