From 15a0e1481d9a1efb3e3aa61cbaf2fa1ba0392d71 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Thu, 20 Dec 2018 19:09:21 -0300 Subject: shader_ir: Initial implementation --- src/video_core/shader/decode/other.cpp | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 src/video_core/shader/decode/other.cpp (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp new file mode 100644 index 000000000..d84702a4f --- /dev/null +++ b/src/video_core/shader/decode/other.cpp @@ -0,0 +1,24 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#include "common/assert.h" +#include "common/common_types.h" +#include "video_core/engines/shader_bytecode.h" +#include "video_core/shader/shader_ir.h" + +namespace VideoCommon::Shader { + +using Tegra::Shader::Instruction; +using Tegra::Shader::OpCode; + +u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { + const Instruction instr = {program_code[pc]}; + const auto opcode = OpCode::Decode(instr); + + UNIMPLEMENTED(); + + return pc; +} + +} // namespace VideoCommon::Shader \ No newline at end of file -- cgit v1.2.3 From cacb934f21d5b2abcbae168f8916bf3e3a21d64b Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Fri, 21 Dec 2018 00:07:32 -0300 Subject: shader_decode: Implement EXIT --- src/video_core/shader/decode/other.cpp | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index d84702a4f..2a5b70b8b 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -16,7 +16,38 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; const auto opcode = OpCode::Decode(instr); - UNIMPLEMENTED(); + switch (opcode->get().GetId()) { + case OpCode::Id::EXIT: { + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "EXIT condition code used: {}", + static_cast(cc)); + + switch (instr.flow.cond) { + case Tegra::Shader::FlowCondition::Always: + bb.push_back(Operation(OperationCode::Exit)); + if (instr.pred.pred_index == static_cast(Tegra::Shader::Pred::UnusedIndex)) { + // If this is an unconditional exit then just end processing here, + // otherwise we have to account for the possibility of the condition + // not being met, so continue processing the next instruction. + pc = MAX_PROGRAM_LENGTH - 1; + } + break; + + case Tegra::Shader::FlowCondition::Fcsm_Tr: + // TODO(bunnei): What is this used for? If we assume this conditon is not + // satisifed, dual vertex shaders in Farming Simulator make more sense + UNIMPLEMENTED_MSG("Skipping unknown FlowCondition::Fcsm_Tr"); + break; + + default: + UNIMPLEMENTED_MSG("Unhandled flow condition: {}", + static_cast(instr.flow.cond.Value())); + } + break; + } + default: + UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName()); + } return pc; } -- cgit v1.2.3 From 4f95dc950ee483ac9d19fb98209abeb26556e26f Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Fri, 21 Dec 2018 00:08:21 -0300 Subject: shader_decode: Implement IPA --- src/video_core/shader/decode/other.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 2a5b70b8b..ffdc77d90 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -45,6 +45,18 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { } break; } + case OpCode::Id::IPA: { + const auto& attribute = instr.attribute.fmt28; + const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), + instr.ipa.sample_mode.Value()}; + + const Node input_attr = GetInputAttribute(attribute.index, attribute.element, input_mode); + const Node ipa = Operation(OperationCode::Ipa, input_attr); + const Node value = GetSaturatedFloat(ipa, instr.ipa.saturate); + + SetRegister(bb, instr.gpr0, value); + break; + } default: UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName()); } -- cgit v1.2.3 From 8215ae942c72ec20c2ebebbf8fc5784e3f21bb3c Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Fri, 21 Dec 2018 00:11:33 -0300 Subject: shader_decode: Partially implement BRA --- src/video_core/shader/decode/other.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index ffdc77d90..3f058324c 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -11,6 +11,7 @@ namespace VideoCommon::Shader { using Tegra::Shader::Instruction; using Tegra::Shader::OpCode; +using Tegra::Shader::ConditionCode; u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; @@ -45,6 +46,17 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { } break; } + case OpCode::Id::BRA: { + UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, + "BRA with constant buffers are not implemented"); + + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF(cc != Tegra::Shader::ConditionCode::T); + + const u32 target = pc + instr.bra.GetBranchTarget(); + bb.push_back(Operation(OperationCode::Bra, Immediate(target))); + break; + } case OpCode::Id::IPA: { const auto& attribute = instr.attribute.fmt28; const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), -- cgit v1.2.3 From 97f33f00cf4076e49f763c8139d388d47a41c84d Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Sat, 15 Dec 2018 03:18:25 -0300 Subject: shader_decode: Implement SSY and SYNC --- src/video_core/shader/decode/other.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 3f058324c..4c2d24202 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -57,6 +57,25 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { bb.push_back(Operation(OperationCode::Bra, Immediate(target))); break; } + case OpCode::Id::SSY: { + UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, + "Constant buffer flow is not supported"); + + // The SSY opcode tells the GPU where to re-converge divergent execution paths, it sets the + // target of the jump that the SYNC instruction will make. The SSY opcode has a similar + // structure to the BRA opcode. + bb.push_back(Operation(OperationCode::Ssy, Immediate(pc + instr.bra.GetBranchTarget()))); + break; + } + case OpCode::Id::SYNC: { + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "SYNC condition code used: {}", + static_cast(cc)); + + // The SYNC opcode jumps to the address previously set by the SSY opcode + bb.push_back(Operation(OperationCode::Sync)); + break; + } case OpCode::Id::IPA: { const auto& attribute = instr.attribute.fmt28; const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), -- cgit v1.2.3 From 9118deb9904f5bb4012d32c8ed63262b3f6e74a3 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Sat, 15 Dec 2018 17:16:14 -0300 Subject: shader_decode: Stub DEPBAR --- src/video_core/shader/decode/other.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 4c2d24202..ef0598d4f 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -88,6 +88,10 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { SetRegister(bb, instr.gpr0, value); break; } + case OpCode::Id::DEPBAR: { + LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed"); + break; + } default: UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName()); } -- cgit v1.2.3 From becfdb863845d9ea81c1844c8ee3c681d03fd9ea Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 17 Dec 2018 17:44:20 -0300 Subject: shader_decode: Implement PBK and BRK --- src/video_core/shader/decode/other.cpp | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index ef0598d4f..0416d7eaa 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -64,7 +64,19 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { // The SSY opcode tells the GPU where to re-converge divergent execution paths, it sets the // target of the jump that the SYNC instruction will make. The SSY opcode has a similar // structure to the BRA opcode. - bb.push_back(Operation(OperationCode::Ssy, Immediate(pc + instr.bra.GetBranchTarget()))); + const u32 target = pc + instr.bra.GetBranchTarget(); + bb.push_back(Operation(OperationCode::Ssy, Immediate(target))); + break; + } + case OpCode::Id::PBK: { + UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, + "Constant buffer PBK is not supported"); + + // PBK pushes to a stack the address where BRK will jump to. This shares stack with SSY but + // using SYNC on a PBK address will kill the shader execution. We don't emulate this because + // it's very unlikely a driver will emit such invalid shader. + const u32 target = pc + instr.bra.GetBranchTarget(); + bb.push_back(Operation(OperationCode::Pbk, Immediate(target))); break; } case OpCode::Id::SYNC: { @@ -76,6 +88,15 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { bb.push_back(Operation(OperationCode::Sync)); break; } + case OpCode::Id::BRK: { + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "BRK condition code used: {}", + static_cast(cc)); + + // The BRK opcode jumps to the address previously set by the PBK opcode + bb.push_back(Operation(OperationCode::Brk)); + break; + } case OpCode::Id::IPA: { const auto& attribute = instr.attribute.fmt28; const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), -- cgit v1.2.3 From 6ca31f544a4559eca547b45b5158d210932cc428 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 17 Dec 2018 19:03:53 -0300 Subject: shader_decode: Implement BRA internal flag --- src/video_core/shader/decode/other.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 0416d7eaa..5b3f9aa30 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -50,11 +50,15 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, "BRA with constant buffers are not implemented"); - const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; - UNIMPLEMENTED_IF(cc != Tegra::Shader::ConditionCode::T); - const u32 target = pc + instr.bra.GetBranchTarget(); - bb.push_back(Operation(OperationCode::Bra, Immediate(target))); + const Node branch = Operation(OperationCode::Bra, Immediate(target)); + + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + if (cc != Tegra::Shader::ConditionCode::T) { + bb.push_back(Conditional(GetConditionCode(cc), {branch})); + } else { + bb.push_back(branch); + } break; } case OpCode::Id::SSY: { -- cgit v1.2.3 From 376a8375118937c577063c5d92ad33cfdc33439b Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 17 Dec 2018 22:18:46 -0300 Subject: shader_decode: Implement MOV_SYS --- src/video_core/shader/decode/other.cpp | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 5b3f9aa30..9200b5da9 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -46,6 +46,33 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { } break; } + case OpCode::Id::KIL: { + UNIMPLEMENTED_IF(instr.flow.cond != Tegra::Shader::FlowCondition::Always); + + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}", + static_cast(cc)); + + bb.push_back(Operation(OperationCode::Kil)); + break; + } + case OpCode::Id::MOV_SYS: { + switch (instr.sys20) { + case Tegra::Shader::SystemVariable::InvocationInfo: { + LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete"); + SetRegister(bb, instr.gpr0, Immediate(0u)); + break; + } + case Tegra::Shader::SystemVariable::Ydirection: { + // Config pack's third value is Y_NEGATE's state. + SetRegister(bb, instr.gpr0, Operation(OperationCode::YNegate)); + break; + } + default: + UNIMPLEMENTED_MSG("Unhandled system move: {}", static_cast(instr.sys20.Value())); + } + break; + } case OpCode::Id::BRA: { UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, "BRA with constant buffers are not implemented"); -- cgit v1.2.3 From 59b34b1d76371bc1bf70ca263a1ac63293a8409e Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Fri, 21 Dec 2018 03:18:54 -0300 Subject: shader_ir: Fixup file inclusions and clang-format --- src/video_core/shader/decode/other.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 9200b5da9..9630ef831 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -9,9 +9,9 @@ namespace VideoCommon::Shader { +using Tegra::Shader::ConditionCode; using Tegra::Shader::Instruction; using Tegra::Shader::OpCode; -using Tegra::Shader::ConditionCode; u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; -- cgit v1.2.3 From e1fea1e0c594cc7c5a404e7006a4b4b2f29200ae Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 24 Dec 2018 02:24:38 -0300 Subject: video_core: Implement IR based geometry shaders --- src/video_core/shader/decode/other.cpp | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 9630ef831..1918762b8 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -12,6 +12,7 @@ namespace VideoCommon::Shader { using Tegra::Shader::ConditionCode; using Tegra::Shader::Instruction; using Tegra::Shader::OpCode; +using Tegra::Shader::Register; u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; @@ -140,6 +141,30 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { SetRegister(bb, instr.gpr0, value); break; } + case OpCode::Id::OUT_R: { + UNIMPLEMENTED_IF_MSG(instr.gpr20.Value() != Register::ZeroIndex, + "Stream buffer is not supported"); + + if (instr.out.emit) { + // gpr0 is used to store the next address and gpr8 contains the address to emit. + // Hardware uses pointers here but we just ignore it + bb.push_back(Operation(OperationCode::EmitVertex)); + SetRegister(bb, instr.gpr0, Immediate(0)); + } + if (instr.out.cut) { + bb.push_back(Operation(OperationCode::EndPrimitive)); + } + break; + } + case OpCode::Id::ISBERD: { + UNIMPLEMENTED_IF(instr.isberd.o != 0); + UNIMPLEMENTED_IF(instr.isberd.skew != 0); + UNIMPLEMENTED_IF(instr.isberd.shift != Tegra::Shader::IsberdShift::None); + UNIMPLEMENTED_IF(instr.isberd.mode != Tegra::Shader::IsberdMode::None); + LOG_WARNING(HW_GPU, "ISBERD instruction is incomplete"); + SetRegister(bb, instr.gpr0, GetRegister(instr.gpr8)); + break; + } case OpCode::Id::DEPBAR: { LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed"); break; -- cgit v1.2.3 From 52223313b10af4c76b516d6ead247a1a201a71d8 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Wed, 26 Dec 2018 02:17:56 -0300 Subject: shader_ir: Remove Ipa primitive --- src/video_core/shader/decode/other.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 1918762b8..386433d8e 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -134,9 +134,8 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), instr.ipa.sample_mode.Value()}; - const Node input_attr = GetInputAttribute(attribute.index, attribute.element, input_mode); - const Node ipa = Operation(OperationCode::Ipa, input_attr); - const Node value = GetSaturatedFloat(ipa, instr.ipa.saturate); + const Node attr = GetInputAttribute(attribute.index, attribute.element, input_mode); + const Node value = GetSaturatedFloat(attr, instr.ipa.saturate); SetRegister(bb, instr.gpr0, value); break; -- cgit v1.2.3 From 50195b1704bcdf22d379d31b143172a32ebdfaec Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Wed, 26 Dec 2018 03:18:11 -0300 Subject: shader_decode: Use proper primitive names --- src/video_core/shader/decode/other.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 386433d8e..6e6795ba7 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -54,7 +54,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}", static_cast(cc)); - bb.push_back(Operation(OperationCode::Kil)); + bb.push_back(Operation(OperationCode::Discard)); break; } case OpCode::Id::MOV_SYS: { @@ -79,7 +79,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { "BRA with constant buffers are not implemented"); const u32 target = pc + instr.bra.GetBranchTarget(); - const Node branch = Operation(OperationCode::Bra, Immediate(target)); + const Node branch = Operation(OperationCode::Branch, Immediate(target)); const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; if (cc != Tegra::Shader::ConditionCode::T) { @@ -97,7 +97,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { // target of the jump that the SYNC instruction will make. The SSY opcode has a similar // structure to the BRA opcode. const u32 target = pc + instr.bra.GetBranchTarget(); - bb.push_back(Operation(OperationCode::Ssy, Immediate(target))); + bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target))); break; } case OpCode::Id::PBK: { @@ -108,7 +108,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { // using SYNC on a PBK address will kill the shader execution. We don't emulate this because // it's very unlikely a driver will emit such invalid shader. const u32 target = pc + instr.bra.GetBranchTarget(); - bb.push_back(Operation(OperationCode::Pbk, Immediate(target))); + bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target))); break; } case OpCode::Id::SYNC: { @@ -117,7 +117,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { static_cast(cc)); // The SYNC opcode jumps to the address previously set by the SSY opcode - bb.push_back(Operation(OperationCode::Sync)); + bb.push_back(Operation(OperationCode::PopFlowStack)); break; } case OpCode::Id::BRK: { @@ -126,7 +126,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { static_cast(cc)); // The BRK opcode jumps to the address previously set by the PBK opcode - bb.push_back(Operation(OperationCode::Brk)); + bb.push_back(Operation(OperationCode::PopFlowStack)); break; } case OpCode::Id::IPA: { -- cgit v1.2.3 From 170c8212bbb10129dfbaed8eb7ab67138c932af2 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Fri, 28 Dec 2018 20:00:36 -0300 Subject: shader_ir: Pass to decoder functions basic block's code --- src/video_core/shader/decode/other.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/video_core/shader/decode/other.cpp') diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 6e6795ba7..c1e5f4efb 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -14,7 +14,7 @@ using Tegra::Shader::Instruction; using Tegra::Shader::OpCode; using Tegra::Shader::Register; -u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { +u32 ShaderIR::DecodeOther(BasicBlock& bb, const BasicBlock& code, u32 pc) { const Instruction instr = {program_code[pc]}; const auto opcode = OpCode::Decode(instr); -- cgit v1.2.3