From f3d1b370aa0fd614cf28f8a609b70906d40da751 Mon Sep 17 00:00:00 2001 From: Fernando Sahmkow Date: Tue, 12 Nov 2019 10:07:22 -0400 Subject: Shader_IR: Implement FLO instruction. --- src/video_core/shader/decode/arithmetic_integer.cpp | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/video_core/shader/decode/arithmetic_integer.cpp') diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index a33d242e9..9208b7bef 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -130,6 +130,24 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { SetRegister(bb, instr.gpr0, value); break; } + case OpCode::Id::FLO_R: + case OpCode::Id::FLO_C: + case OpCode::Id::FLO_IMM: { + Node value; + if (instr.flo.invert) { + op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); + } + if (instr.flo.is_signed) { + value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b); + } else { + value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b); + } + if (instr.flo.sh) { + value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31)); + } + SetRegister(bb, instr.gpr0, value); + break; + } case OpCode::Id::SEL_C: case OpCode::Id::SEL_R: case OpCode::Id::SEL_IMM: { -- cgit v1.2.3 From c8473f399e745993d2b9980f4ef62fa6a208ec3d Mon Sep 17 00:00:00 2001 From: Fernando Sahmkow Date: Mon, 18 Nov 2019 07:34:34 -0400 Subject: Shader_IR: Address Feedback --- src/video_core/shader/decode/arithmetic_integer.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src/video_core/shader/decode/arithmetic_integer.cpp') diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index 9208b7bef..371fae127 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -135,17 +135,18 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { case OpCode::Id::FLO_IMM: { Node value; if (instr.flo.invert) { - op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); + op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_b)); } if (instr.flo.is_signed) { - value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b); + value = Operation(OperationCode::IBitMSB, NO_PRECISE, std::move(op_b)); } else { - value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b); + value = Operation(OperationCode::UBitMSB, NO_PRECISE, std::move(op_b)); } if (instr.flo.sh) { - value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31)); + value = + Operation(OperationCode::UBitwiseXor, NO_PRECISE, std::move(value), Immediate(31)); } - SetRegister(bb, instr.gpr0, value); + SetRegister(bb, instr.gpr0, std::move(value)); break; } case OpCode::Id::SEL_C: -- cgit v1.2.3