From 9531a2928369bcc094c28b77408811d47c46c7f2 Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Sat, 21 Apr 2018 19:19:33 -0500
Subject: GPU: Support multiple enabled vertex arrays.

The vertex arrays will be copied to the stream buffer one after the other, and the attributes will be set using the ARB_vertex_attrib_binding extension.

yuzu now thus requires OpenGL 4.3 or the ARB_vertex_attrib_binding extension.
---
 src/video_core/engines/maxwell_3d.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index d4fcedace..609504795 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -500,6 +500,11 @@ public:
                         return static_cast<GPUVAddr>((static_cast<GPUVAddr>(start_high) << 32) |
                                                      start_low);
                     }
+
+                    bool IsEnabled() const {
+                        return enable != 0 && StartAddress() != 0;
+                    }
+
                 } vertex_array[NumVertexArrays];
 
                 Blend blend;
-- 
cgit v1.2.3


From f20895358525f3a8abaefe3a5c2ebe7d30eadc78 Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 23 Apr 2018 17:06:57 -0500
Subject: GPU: Added asserts to our code for handling the QUERY_GET GPU
 command.

This is based on research from nouveau. Many things are currently unknown and will require hwtests in the future.
This commit also stubs QueryMode::Write2 to do the same as Write. Nouveau code treats them interchangeably, it is currently unknown what the difference is.
---
 src/video_core/engines/maxwell_3d.cpp | 27 ++++++++++++++++++++++++++-
 src/video_core/engines/maxwell_3d.h   | 28 +++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 2 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 2a3ff234a..35773a695 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -147,11 +147,36 @@ void Maxwell3D::ProcessQueryGet() {
     // VAddr before writing.
     VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address);
 
+    // TODO(Subv): Support the other query units.
+    ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
+               "Units other than CROP are unimplemented");
+    ASSERT_MSG(regs.query.query_get.short_query,
+               "Writing the entire query result structure is unimplemented");
+
+    u32 value = Memory::Read32(address);
+    u32 result = 0;
+
+    // TODO(Subv): Support the other query variables
+    switch (regs.query.query_get.select) {
+    case Regs::QuerySelect::Zero:
+        result = 0;
+        break;
+    default:
+        UNIMPLEMENTED_MSG("Unimplemented query select type %u",
+                          static_cast<u32>(regs.query.query_get.select.Value()));
+    }
+
+    // TODO(Subv): Research and implement how query sync conditions work.
+
     switch (regs.query.query_get.mode) {
-    case Regs::QueryMode::Write: {
+    case Regs::QueryMode::Write:
+    case Regs::QueryMode::Write2: {
         // Write the current query sequence to the sequence address.
         u32 sequence = regs.query.query_sequence;
         Memory::Write32(address, sequence);
+
+        // TODO(Subv): Write the proper query response structure to the address when not using short
+        // mode.
         break;
     }
     default:
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index d4fcedace..5ee581acf 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -46,6 +46,29 @@ public:
         enum class QueryMode : u32 {
             Write = 0,
             Sync = 1,
+            // TODO(Subv): It is currently unknown what the difference between method 2 and method 0
+            // is.
+            Write2 = 2,
+        };
+
+        enum class QueryUnit : u32 {
+            VFetch = 1,
+            VP = 2,
+            Rast = 4,
+            StrmOut = 5,
+            GP = 6,
+            ZCull = 7,
+            Prop = 10,
+            Crop = 15,
+        };
+
+        enum class QuerySelect : u32 {
+            Zero = 0,
+        };
+
+        enum class QuerySyncCondition : u32 {
+            NotEqual = 0,
+            GreaterThan = 1,
         };
 
         enum class ShaderProgram : u32 {
@@ -476,7 +499,10 @@ public:
                         u32 raw;
                         BitField<0, 2, QueryMode> mode;
                         BitField<4, 1, u32> fence;
-                        BitField<12, 4, u32> unit;
+                        BitField<12, 4, QueryUnit> unit;
+                        BitField<16, 1, QuerySyncCondition> sync_cond;
+                        BitField<23, 5, QuerySelect> select;
+                        BitField<28, 1, u32> short_query;
                     } query_get;
 
                     GPUVAddr QueryAddress() const {
-- 
cgit v1.2.3


From 9e11a76e926a7190880063d8fc8c3d97003b9938 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Sat, 21 Apr 2018 11:16:21 -0400
Subject: memory_manager: Use GPUVAdddr, not PAddr, for GPU addresses.

---
 src/video_core/command_processor.cpp               |  4 +-
 src/video_core/engines/maxwell_3d.cpp              | 11 ++--
 src/video_core/memory_manager.cpp                  | 72 +++++++++++-----------
 src/video_core/memory_manager.h                    | 16 ++---
 src/video_core/renderer_opengl/gl_rasterizer.cpp   |  6 +-
 .../renderer_opengl/gl_rasterizer_cache.cpp        |  4 +-
 src/yuzu/debugger/graphics/graphics_surface.cpp    |  4 +-
 7 files changed, 57 insertions(+), 60 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index d4cdb4ab2..7850ae103 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -90,9 +90,7 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
 }
 
 void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
-    // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
-    // application VAddr.
-    const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
+    const VAddr head_address = memory_manager->GpuToCpuAddress(address);
     VAddr current_addr = head_address;
     while (current_addr < head_address + size * sizeof(CommandHeader)) {
         const CommandHeader header = {Memory::Read32(current_addr)};
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 35773a695..8d7d627b8 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -145,7 +145,7 @@ void Maxwell3D::ProcessQueryGet() {
     GPUVAddr sequence_address = regs.query.QueryAddress();
     // Since the sequence address is given as a GPU VAddr, we have to convert it to an application
     // VAddr before writing.
-    VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address);
+    VAddr address = memory_manager.GpuToCpuAddress(sequence_address);
 
     // TODO(Subv): Support the other query units.
     ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
@@ -225,8 +225,7 @@ void Maxwell3D::ProcessCBData(u32 value) {
     // Don't allow writing past the end of the buffer.
     ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
 
-    VAddr address =
-        memory_manager.PhysicalToVirtualAddress(buffer_address + regs.const_buffer.cb_pos);
+    VAddr address = memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
 
     Memory::Write32(address, value);
 
@@ -238,7 +237,7 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
     GPUVAddr tic_base_address = regs.tic.TICAddress();
 
     GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
-    VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
+    VAddr tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
 
     Texture::TICEntry tic_entry;
     Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
@@ -268,7 +267,7 @@ Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
     GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
 
     GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
-    VAddr tsc_address_cpu = memory_manager.PhysicalToVirtualAddress(tsc_address_gpu);
+    VAddr tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
 
     Texture::TSCEntry tsc_entry;
     Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
@@ -293,7 +292,7 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
          current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
 
         Texture::TextureHandle tex_handle{
-            Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
+            Memory::Read32(memory_manager.GpuToCpuAddress(current_texture))};
 
         Texture::FullTextureInfo tex_info{};
         // TODO(Subv): Use the shader to determine which textures are actually accessed.
diff --git a/src/video_core/memory_manager.cpp b/src/video_core/memory_manager.cpp
index 2e1edee03..3f21071c0 100644
--- a/src/video_core/memory_manager.cpp
+++ b/src/video_core/memory_manager.cpp
@@ -8,90 +8,90 @@
 
 namespace Tegra {
 
-PAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
-    boost::optional<PAddr> paddr = FindFreeBlock(size, align);
-    ASSERT(paddr);
+GPUVAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
+    boost::optional<GPUVAddr> gpu_addr = FindFreeBlock(size, align);
+    ASSERT(gpu_addr);
 
     for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
-        ASSERT(PageSlot(*paddr + offset) == static_cast<u64>(PageStatus::Unmapped));
-        PageSlot(*paddr + offset) = static_cast<u64>(PageStatus::Allocated);
+        ASSERT(PageSlot(*gpu_addr + offset) == static_cast<u64>(PageStatus::Unmapped));
+        PageSlot(*gpu_addr + offset) = static_cast<u64>(PageStatus::Allocated);
     }
 
-    return *paddr;
+    return *gpu_addr;
 }
 
-PAddr MemoryManager::AllocateSpace(PAddr paddr, u64 size, u64 align) {
+GPUVAddr MemoryManager::AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align) {
     for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
-        ASSERT(PageSlot(paddr + offset) == static_cast<u64>(PageStatus::Unmapped));
-        PageSlot(paddr + offset) = static_cast<u64>(PageStatus::Allocated);
+        ASSERT(PageSlot(gpu_addr + offset) == static_cast<u64>(PageStatus::Unmapped));
+        PageSlot(gpu_addr + offset) = static_cast<u64>(PageStatus::Allocated);
     }
 
-    return paddr;
+    return gpu_addr;
 }
 
-PAddr MemoryManager::MapBufferEx(VAddr vaddr, u64 size) {
-    boost::optional<PAddr> paddr = FindFreeBlock(size, PAGE_SIZE);
-    ASSERT(paddr);
+GPUVAddr MemoryManager::MapBufferEx(VAddr cpu_addr, u64 size) {
+    boost::optional<GPUVAddr> gpu_addr = FindFreeBlock(size, PAGE_SIZE);
+    ASSERT(gpu_addr);
 
     for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
-        ASSERT(PageSlot(*paddr + offset) == static_cast<u64>(PageStatus::Unmapped));
-        PageSlot(*paddr + offset) = vaddr + offset;
+        ASSERT(PageSlot(*gpu_addr + offset) == static_cast<u64>(PageStatus::Unmapped));
+        PageSlot(*gpu_addr + offset) = cpu_addr + offset;
     }
 
-    return *paddr;
+    return *gpu_addr;
 }
 
-PAddr MemoryManager::MapBufferEx(VAddr vaddr, PAddr paddr, u64 size) {
-    ASSERT((paddr & PAGE_MASK) == 0);
+GPUVAddr MemoryManager::MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size) {
+    ASSERT((gpu_addr & PAGE_MASK) == 0);
 
     for (u64 offset = 0; offset < size; offset += PAGE_SIZE) {
-        ASSERT(PageSlot(paddr + offset) == static_cast<u64>(PageStatus::Allocated));
-        PageSlot(paddr + offset) = vaddr + offset;
+        ASSERT(PageSlot(gpu_addr + offset) == static_cast<u64>(PageStatus::Allocated));
+        PageSlot(gpu_addr + offset) = cpu_addr + offset;
     }
 
-    return paddr;
+    return gpu_addr;
 }
 
-boost::optional<PAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) {
-    PAddr paddr = 0;
+boost::optional<GPUVAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) {
+    GPUVAddr gpu_addr = 0;
     u64 free_space = 0;
     align = (align + PAGE_MASK) & ~PAGE_MASK;
 
-    while (paddr + free_space < MAX_ADDRESS) {
-        if (!IsPageMapped(paddr + free_space)) {
+    while (gpu_addr + free_space < MAX_ADDRESS) {
+        if (!IsPageMapped(gpu_addr + free_space)) {
             free_space += PAGE_SIZE;
             if (free_space >= size) {
-                return paddr;
+                return gpu_addr;
             }
         } else {
-            paddr += free_space + PAGE_SIZE;
+            gpu_addr += free_space + PAGE_SIZE;
             free_space = 0;
-            paddr = Common::AlignUp(paddr, align);
+            gpu_addr = Common::AlignUp(gpu_addr, align);
         }
     }
 
     return {};
 }
 
-VAddr MemoryManager::PhysicalToVirtualAddress(PAddr paddr) {
-    VAddr base_addr = PageSlot(paddr);
+VAddr MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) {
+    VAddr base_addr = PageSlot(gpu_addr);
     ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped));
-    return base_addr + (paddr & PAGE_MASK);
+    return base_addr + (gpu_addr & PAGE_MASK);
 }
 
-bool MemoryManager::IsPageMapped(PAddr paddr) {
-    return PageSlot(paddr) != static_cast<u64>(PageStatus::Unmapped);
+bool MemoryManager::IsPageMapped(GPUVAddr gpu_addr) {
+    return PageSlot(gpu_addr) != static_cast<u64>(PageStatus::Unmapped);
 }
 
-VAddr& MemoryManager::PageSlot(PAddr paddr) {
-    auto& block = page_table[(paddr >> (PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK];
+VAddr& MemoryManager::PageSlot(GPUVAddr gpu_addr) {
+    auto& block = page_table[(gpu_addr >> (PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK];
     if (!block) {
         block = std::make_unique<PageBlock>();
         for (unsigned index = 0; index < PAGE_BLOCK_SIZE; index++) {
             (*block)[index] = static_cast<u64>(PageStatus::Unmapped);
         }
     }
-    return (*block)[(paddr >> PAGE_BITS) & PAGE_BLOCK_MASK];
+    return (*block)[(gpu_addr >> PAGE_BITS) & PAGE_BLOCK_MASK];
 }
 
 } // namespace Tegra
diff --git a/src/video_core/memory_manager.h b/src/video_core/memory_manager.h
index b73e283f8..4710cb21f 100644
--- a/src/video_core/memory_manager.h
+++ b/src/video_core/memory_manager.h
@@ -18,20 +18,20 @@ class MemoryManager final {
 public:
     MemoryManager() = default;
 
-    PAddr AllocateSpace(u64 size, u64 align);
-    PAddr AllocateSpace(PAddr paddr, u64 size, u64 align);
-    PAddr MapBufferEx(VAddr vaddr, u64 size);
-    PAddr MapBufferEx(VAddr vaddr, PAddr paddr, u64 size);
-    VAddr PhysicalToVirtualAddress(PAddr paddr);
+    GPUVAddr AllocateSpace(u64 size, u64 align);
+    GPUVAddr AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align);
+    GPUVAddr MapBufferEx(VAddr cpu_addr, u64 size);
+    GPUVAddr MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size);
+    VAddr GpuToCpuAddress(GPUVAddr gpu_addr);
 
     static constexpr u64 PAGE_BITS = 16;
     static constexpr u64 PAGE_SIZE = 1 << PAGE_BITS;
     static constexpr u64 PAGE_MASK = PAGE_SIZE - 1;
 
 private:
-    boost::optional<PAddr> FindFreeBlock(u64 size, u64 align = 1);
-    bool IsPageMapped(PAddr paddr);
-    VAddr& PageSlot(PAddr paddr);
+    boost::optional<GPUVAddr> FindFreeBlock(u64 size, u64 align = 1);
+    bool IsPageMapped(GPUVAddr gpu_addr);
+    VAddr& PageSlot(GPUVAddr gpu_addr);
 
     enum class PageStatus : u64 {
         Unmapped = 0xFFFFFFFFFFFFFFFFULL,
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index 82001e7b4..8568d6762 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -233,7 +233,7 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset) {
         // Fetch program code from memory
         GLShader::ProgramCode program_code;
         const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset};
-        const VAddr cpu_address{gpu.memory_manager.PhysicalToVirtualAddress(gpu_address)};
+        const VAddr cpu_address{gpu.memory_manager.GpuToCpuAddress(gpu_address)};
         Memory::ReadBlock(cpu_address, program_code.data(), program_code.size() * sizeof(u64));
         GLShader::ShaderSetup setup{std::move(program_code)};
 
@@ -395,7 +395,7 @@ void RasterizerOpenGL::DrawArrays() {
     if (is_indexed) {
         const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
         const VAddr index_data_addr{
-            memory_manager->PhysicalToVirtualAddress(regs.index_array.StartAddress())};
+            memory_manager->GpuToCpuAddress(regs.index_array.StartAddress())};
         Memory::ReadBlock(index_data_addr, offseted_buffer, index_buffer_size);
 
         index_buffer_offset = buffer_offset;
@@ -659,7 +659,7 @@ u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, GLuint progr
         buffer_draw_state.enabled = true;
         buffer_draw_state.bindpoint = current_bindpoint + bindpoint;
 
-        VAddr addr = gpu.memory_manager->PhysicalToVirtualAddress(buffer.address);
+        VAddr addr = gpu.memory_manager->GpuToCpuAddress(buffer.address);
         std::vector<u8> data(used_buffer.GetSize() * sizeof(float));
         Memory::ReadBlock(addr, data.data(), data.size());
 
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 7410471cc..46f0f25aa 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -1028,7 +1028,7 @@ Surface RasterizerCacheOpenGL::GetTextureSurface(const Tegra::Texture::FullTextu
     auto& gpu = Core::System::GetInstance().GPU();
 
     SurfaceParams params;
-    params.addr = gpu.memory_manager->PhysicalToVirtualAddress(config.tic.Address());
+    params.addr = gpu.memory_manager->GpuToCpuAddress(config.tic.Address());
     params.width = config.tic.Width();
     params.height = config.tic.Height();
     params.is_tiled = config.tic.IsTiled();
@@ -1106,7 +1106,7 @@ SurfaceSurfaceRect_Tuple RasterizerCacheOpenGL::GetFramebufferSurfaces(
     color_params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
     SurfaceParams depth_params = color_params;
 
-    color_params.addr = memory_manager->PhysicalToVirtualAddress(config.Address());
+    color_params.addr = memory_manager->GpuToCpuAddress(config.Address());
     color_params.pixel_format = SurfaceParams::PixelFormatFromRenderTargetFormat(config.format);
     color_params.component_type = SurfaceParams::ComponentTypeFromRenderTarget(config.format);
     color_params.UpdateParams();
diff --git a/src/yuzu/debugger/graphics/graphics_surface.cpp b/src/yuzu/debugger/graphics/graphics_surface.cpp
index 5fada74be..5cadb807e 100644
--- a/src/yuzu/debugger/graphics/graphics_surface.cpp
+++ b/src/yuzu/debugger/graphics/graphics_surface.cpp
@@ -378,7 +378,7 @@ void GraphicsSurfaceWidget::OnUpdate() {
     // TODO: Implement a good way to visualize alpha components!
 
     QImage decoded_image(surface_width, surface_height, QImage::Format_ARGB32);
-    VAddr address = gpu.memory_manager->PhysicalToVirtualAddress(surface_address);
+    VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address);
 
     auto unswizzled_data =
         Tegra::Texture::UnswizzleTexture(address, surface_format, surface_width, surface_height);
@@ -437,7 +437,7 @@ void GraphicsSurfaceWidget::SaveSurface() {
             pixmap->save(&file, "PNG");
     } else if (selectedFilter == bin_filter) {
         auto& gpu = Core::System::GetInstance().GPU();
-        VAddr address = gpu.memory_manager->PhysicalToVirtualAddress(surface_address);
+        VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address);
 
         const u8* buffer = Memory::GetPointer(address);
         ASSERT_MSG(buffer != nullptr, "Memory not accessible");
-- 
cgit v1.2.3


From 239ac8abe228b9080741ba7d50d9e13cc4a1ceae Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Sat, 21 Apr 2018 12:31:30 -0400
Subject: memory_manager: Make GpuToCpuAddress return an optional.

---
 src/video_core/command_processor.cpp                |  6 +++---
 src/video_core/engines/maxwell_3d.cpp               | 21 +++++++++++----------
 src/video_core/memory_manager.cpp                   |  7 ++++++-
 src/video_core/memory_manager.h                     |  5 ++++-
 src/video_core/renderer_opengl/gl_rasterizer.cpp    | 14 +++++++-------
 .../renderer_opengl/gl_rasterizer_cache.cpp         |  4 ++--
 src/yuzu/debugger/graphics/graphics_surface.cpp     |  8 ++++----
 7 files changed, 37 insertions(+), 28 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 7850ae103..2c04daba3 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -90,9 +90,9 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
 }
 
 void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
-    const VAddr head_address = memory_manager->GpuToCpuAddress(address);
-    VAddr current_addr = head_address;
-    while (current_addr < head_address + size * sizeof(CommandHeader)) {
+    const boost::optional<VAddr> head_address = memory_manager->GpuToCpuAddress(address);
+    VAddr current_addr = *head_address;
+    while (current_addr < *head_address + size * sizeof(CommandHeader)) {
         const CommandHeader header = {Memory::Read32(current_addr)};
         current_addr += sizeof(u32);
 
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 8d7d627b8..4e9aed380 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -145,7 +145,7 @@ void Maxwell3D::ProcessQueryGet() {
     GPUVAddr sequence_address = regs.query.QueryAddress();
     // Since the sequence address is given as a GPU VAddr, we have to convert it to an application
     // VAddr before writing.
-    VAddr address = memory_manager.GpuToCpuAddress(sequence_address);
+    boost::optional<VAddr> address = memory_manager.GpuToCpuAddress(sequence_address);
 
     // TODO(Subv): Support the other query units.
     ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
@@ -153,7 +153,7 @@ void Maxwell3D::ProcessQueryGet() {
     ASSERT_MSG(regs.query.query_get.short_query,
                "Writing the entire query result structure is unimplemented");
 
-    u32 value = Memory::Read32(address);
+    u32 value = Memory::Read32(*address);
     u32 result = 0;
 
     // TODO(Subv): Support the other query variables
@@ -173,7 +173,7 @@ void Maxwell3D::ProcessQueryGet() {
     case Regs::QueryMode::Write2: {
         // Write the current query sequence to the sequence address.
         u32 sequence = regs.query.query_sequence;
-        Memory::Write32(address, sequence);
+        Memory::Write32(*address, sequence);
 
         // TODO(Subv): Write the proper query response structure to the address when not using short
         // mode.
@@ -225,9 +225,10 @@ void Maxwell3D::ProcessCBData(u32 value) {
     // Don't allow writing past the end of the buffer.
     ASSERT(regs.const_buffer.cb_pos + sizeof(u32) <= regs.const_buffer.cb_size);
 
-    VAddr address = memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
+    boost::optional<VAddr> address =
+        memory_manager.GpuToCpuAddress(buffer_address + regs.const_buffer.cb_pos);
 
-    Memory::Write32(address, value);
+    Memory::Write32(*address, value);
 
     // Increment the current buffer position.
     regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
@@ -237,10 +238,10 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
     GPUVAddr tic_base_address = regs.tic.TICAddress();
 
     GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
-    VAddr tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
+    boost::optional<VAddr> tic_address_cpu = memory_manager.GpuToCpuAddress(tic_address_gpu);
 
     Texture::TICEntry tic_entry;
-    Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
+    Memory::ReadBlock(*tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
 
     ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear ||
                    tic_entry.header_version == Texture::TICHeaderVersion::Pitch,
@@ -267,10 +268,10 @@ Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
     GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
 
     GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
-    VAddr tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
+    boost::optional<VAddr> tsc_address_cpu = memory_manager.GpuToCpuAddress(tsc_address_gpu);
 
     Texture::TSCEntry tsc_entry;
-    Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
+    Memory::ReadBlock(*tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
     return tsc_entry;
 }
 
@@ -292,7 +293,7 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
          current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
 
         Texture::TextureHandle tex_handle{
-            Memory::Read32(memory_manager.GpuToCpuAddress(current_texture))};
+            Memory::Read32(*memory_manager.GpuToCpuAddress(current_texture))};
 
         Texture::FullTextureInfo tex_info{};
         // TODO(Subv): Use the shader to determine which textures are actually accessed.
diff --git a/src/video_core/memory_manager.cpp b/src/video_core/memory_manager.cpp
index 3f21071c0..9bbbb7e65 100644
--- a/src/video_core/memory_manager.cpp
+++ b/src/video_core/memory_manager.cpp
@@ -73,9 +73,14 @@ boost::optional<GPUVAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) {
     return {};
 }
 
-VAddr MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) {
+boost::optional<VAddr> MemoryManager::GpuToCpuAddress(GPUVAddr gpu_addr) {
     VAddr base_addr = PageSlot(gpu_addr);
     ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped));
+
+    if (base_addr == static_cast<u64>(PageStatus::Allocated)) {
+        return {};
+    }
+
     return base_addr + (gpu_addr & PAGE_MASK);
 }
 
diff --git a/src/video_core/memory_manager.h b/src/video_core/memory_manager.h
index 4710cb21f..246c8fb7e 100644
--- a/src/video_core/memory_manager.h
+++ b/src/video_core/memory_manager.h
@@ -6,6 +6,9 @@
 
 #include <array>
 #include <memory>
+
+#include <boost/optional.hpp>
+
 #include "common/common_types.h"
 #include "core/memory.h"
 
@@ -22,7 +25,7 @@ public:
     GPUVAddr AllocateSpace(GPUVAddr gpu_addr, u64 size, u64 align);
     GPUVAddr MapBufferEx(VAddr cpu_addr, u64 size);
     GPUVAddr MapBufferEx(VAddr cpu_addr, GPUVAddr gpu_addr, u64 size);
-    VAddr GpuToCpuAddress(GPUVAddr gpu_addr);
+    boost::optional<VAddr> GpuToCpuAddress(GPUVAddr gpu_addr);
 
     static constexpr u64 PAGE_BITS = 16;
     static constexpr u64 PAGE_SIZE = 1 << PAGE_BITS;
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index 8568d6762..71612790b 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -150,7 +150,7 @@ std::pair<u8*, GLintptr> RasterizerOpenGL::SetupVertexArrays(u8* array_ptr,
         u64 size = end - start + 1;
 
         // Copy vertex array data
-        const VAddr data_addr{memory_manager->PhysicalToVirtualAddress(start)};
+        const VAddr data_addr{*memory_manager->GpuToCpuAddress(start)};
         res_cache.FlushRegion(data_addr, size, nullptr);
         Memory::ReadBlock(data_addr, array_ptr, size);
 
@@ -233,8 +233,8 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset) {
         // Fetch program code from memory
         GLShader::ProgramCode program_code;
         const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset};
-        const VAddr cpu_address{gpu.memory_manager.GpuToCpuAddress(gpu_address)};
-        Memory::ReadBlock(cpu_address, program_code.data(), program_code.size() * sizeof(u64));
+        const boost::optional<VAddr> cpu_address{gpu.memory_manager.GpuToCpuAddress(gpu_address)};
+        Memory::ReadBlock(*cpu_address, program_code.data(), program_code.size() * sizeof(u64));
         GLShader::ShaderSetup setup{std::move(program_code)};
 
         GLShader::ShaderEntries shader_resources;
@@ -394,9 +394,9 @@ void RasterizerOpenGL::DrawArrays() {
     GLintptr index_buffer_offset = 0;
     if (is_indexed) {
         const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
-        const VAddr index_data_addr{
+        const boost::optional<VAddr> index_data_addr{
             memory_manager->GpuToCpuAddress(regs.index_array.StartAddress())};
-        Memory::ReadBlock(index_data_addr, offseted_buffer, index_buffer_size);
+        Memory::ReadBlock(*index_data_addr, offseted_buffer, index_buffer_size);
 
         index_buffer_offset = buffer_offset;
         offseted_buffer += index_buffer_size;
@@ -659,9 +659,9 @@ u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, GLuint progr
         buffer_draw_state.enabled = true;
         buffer_draw_state.bindpoint = current_bindpoint + bindpoint;
 
-        VAddr addr = gpu.memory_manager->GpuToCpuAddress(buffer.address);
+        boost::optional<VAddr> addr = gpu.memory_manager->GpuToCpuAddress(buffer.address);
         std::vector<u8> data(used_buffer.GetSize() * sizeof(float));
-        Memory::ReadBlock(addr, data.data(), data.size());
+        Memory::ReadBlock(*addr, data.data(), data.size());
 
         glBindBuffer(GL_SHADER_STORAGE_BUFFER, buffer_draw_state.ssbo);
         glBufferData(GL_SHADER_STORAGE_BUFFER, data.size(), data.data(), GL_DYNAMIC_DRAW);
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 46f0f25aa..ced648c12 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -1028,7 +1028,7 @@ Surface RasterizerCacheOpenGL::GetTextureSurface(const Tegra::Texture::FullTextu
     auto& gpu = Core::System::GetInstance().GPU();
 
     SurfaceParams params;
-    params.addr = gpu.memory_manager->GpuToCpuAddress(config.tic.Address());
+    params.addr = *gpu.memory_manager->GpuToCpuAddress(config.tic.Address());
     params.width = config.tic.Width();
     params.height = config.tic.Height();
     params.is_tiled = config.tic.IsTiled();
@@ -1106,7 +1106,7 @@ SurfaceSurfaceRect_Tuple RasterizerCacheOpenGL::GetFramebufferSurfaces(
     color_params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
     SurfaceParams depth_params = color_params;
 
-    color_params.addr = memory_manager->GpuToCpuAddress(config.Address());
+    color_params.addr = *memory_manager->GpuToCpuAddress(config.Address());
     color_params.pixel_format = SurfaceParams::PixelFormatFromRenderTargetFormat(config.format);
     color_params.component_type = SurfaceParams::ComponentTypeFromRenderTarget(config.format);
     color_params.UpdateParams();
diff --git a/src/yuzu/debugger/graphics/graphics_surface.cpp b/src/yuzu/debugger/graphics/graphics_surface.cpp
index 5cadb807e..1fbca8ad0 100644
--- a/src/yuzu/debugger/graphics/graphics_surface.cpp
+++ b/src/yuzu/debugger/graphics/graphics_surface.cpp
@@ -378,10 +378,10 @@ void GraphicsSurfaceWidget::OnUpdate() {
     // TODO: Implement a good way to visualize alpha components!
 
     QImage decoded_image(surface_width, surface_height, QImage::Format_ARGB32);
-    VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address);
+    boost::optional<VAddr> address = gpu.memory_manager->GpuToCpuAddress(surface_address);
 
     auto unswizzled_data =
-        Tegra::Texture::UnswizzleTexture(address, surface_format, surface_width, surface_height);
+        Tegra::Texture::UnswizzleTexture(*address, surface_format, surface_width, surface_height);
 
     auto texture_data = Tegra::Texture::DecodeTexture(unswizzled_data, surface_format,
                                                       surface_width, surface_height);
@@ -437,9 +437,9 @@ void GraphicsSurfaceWidget::SaveSurface() {
             pixmap->save(&file, "PNG");
     } else if (selectedFilter == bin_filter) {
         auto& gpu = Core::System::GetInstance().GPU();
-        VAddr address = gpu.memory_manager->GpuToCpuAddress(surface_address);
+        boost::optional<VAddr> address = gpu.memory_manager->GpuToCpuAddress(surface_address);
 
-        const u8* buffer = Memory::GetPointer(address);
+        const u8* buffer = Memory::GetPointer(*address);
         ASSERT_MSG(buffer != nullptr, "Memory not accessible");
 
         QFile file(filename);
-- 
cgit v1.2.3


From 0369ee72484c42983185d8d50fe6db13607fb599 Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Tue, 24 Apr 2018 22:42:54 -0500
Subject: Shaders: Added decodings for the FSET instructions.

---
 src/video_core/engines/shader_bytecode.h           | 37 +++++++++++++++++-----
 .../renderer_opengl/gl_shader_decompiler.cpp       |  2 +-
 2 files changed, 30 insertions(+), 9 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 5a006aee5..6cae6ff45 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -214,6 +214,20 @@ union Instruction {
         BitField<56, 1, u64> neg_b;
     } fsetp;
 
+    union {
+        BitField<39, 3, u64> pred39;
+        BitField<42, 1, u64> neg_pred;
+        BitField<43, 1, u64> neg_a;
+        BitField<44, 1, u64> abs_b;
+        BitField<45, 2, PredOperation> op;
+        BitField<48, 4, PredCondition> cond;
+        BitField<53, 1, u64> neg_b;
+        BitField<54, 1, u64> abs_a;
+        BitField<52, 1, u64> bf;
+        BitField<55, 1, u64> ftz;
+        BitField<56, 1, u64> neg_imm;
+    } fset;
+
     BitField<61, 1, u64> is_b_imm;
     BitField<60, 1, u64> is_b_gpr;
     BitField<59, 1, u64> is_c_gpr;
@@ -272,6 +286,9 @@ public:
         FSETP_C, // Set Predicate
         FSETP_R,
         FSETP_IMM,
+        FSET_C,
+        FSET_R,
+        FSET_IMM,
         ISETP_C,
         ISETP_IMM,
         ISETP_R,
@@ -283,8 +300,9 @@ public:
         Ffma,
         Flow,
         Memory,
-        FloatPredicate,
-        IntegerPredicate,
+        FloatSet,
+        FloatSetPredicate,
+        IntegerSetPredicate,
         Unknown,
     };
 
@@ -417,12 +435,15 @@ private:
             INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
             INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
             INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
-            INST("010010111011----", Id::FSETP_C, Type::FloatPredicate, "FSETP_C"),
-            INST("010110111011----", Id::FSETP_R, Type::FloatPredicate, "FSETP_R"),
-            INST("0011011-1011----", Id::FSETP_IMM, Type::FloatPredicate, "FSETP_IMM"),
-            INST("010010110110----", Id::ISETP_C, Type::IntegerPredicate, "ISETP_C"),
-            INST("010110110110----", Id::ISETP_R, Type::IntegerPredicate, "ISETP_R"),
-            INST("0011011-0110----", Id::ISETP_IMM, Type::IntegerPredicate, "ISETP_IMM"),
+            INST("01011000--------", Id::FSET_R, Type::FloatSet, "FSET_R"),
+            INST("0100100---------", Id::FSET_C, Type::FloatSet, "FSET_C"),
+            INST("0011000---------", Id::FSET_IMM, Type::FloatSet, "FSET_IMM"),
+            INST("010010111011----", Id::FSETP_C, Type::FloatSetPredicate, "FSETP_C"),
+            INST("010110111011----", Id::FSETP_R, Type::FloatSetPredicate, "FSETP_R"),
+            INST("0011011-1011----", Id::FSETP_IMM, Type::FloatSetPredicate, "FSETP_IMM"),
+            INST("010010110110----", Id::ISETP_C, Type::IntegerSetPredicate, "ISETP_C"),
+            INST("010110110110----", Id::ISETP_R, Type::IntegerSetPredicate, "ISETP_R"),
+            INST("0011011-0110----", Id::ISETP_IMM, Type::IntegerSetPredicate, "ISETP_IMM"),
         };
 #undef INST
         std::stable_sort(table.begin(), table.end(), [](const auto& a, const auto& b) {
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 086424395..896b6cd2c 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -519,7 +519,7 @@ private:
             }
             break;
         }
-        case OpCode::Type::FloatPredicate: {
+        case OpCode::Type::FloatSetPredicate: {
             std::string op_a = instr.fsetp.neg_a ? "-" : "";
             op_a += GetRegister(instr.gpr8);
 
-- 
cgit v1.2.3


From b7551e457bacf972789136cfdc1e90c5a2e0dae6 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Wed, 25 Apr 2018 08:13:44 -0400
Subject: video-core: Move logging macros over to new fmt-capable ones

---
 src/video_core/command_processor.cpp               | 12 +++++++-----
 src/video_core/engines/maxwell_3d.cpp              |  4 ++--
 src/video_core/renderer_opengl/gl_rasterizer.cpp   |  6 +++---
 src/video_core/renderer_opengl/renderer_opengl.cpp | 10 +++++-----
 src/video_core/video_core.cpp                      |  6 +++---
 5 files changed, 20 insertions(+), 18 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 2c04daba3..f6a88f031 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -31,12 +31,14 @@ enum class BufferMethods {
 };
 
 void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params) {
-    LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X remaining params %u",
-                method, subchannel, value, remaining_params);
+    NGLOG_WARNING(HW_GPU,
+                  "Processing method {:08X} on subchannel {} value "
+                  "{:08X} remaining params {}",
+                  method, subchannel, value, remaining_params);
 
     if (method == static_cast<u32>(BufferMethods::SetGraphMacroEntry)) {
         // Prepare to upload a new macro, reset the upload counter.
-        LOG_DEBUG(HW_GPU, "Uploading GPU macro %08X", value);
+        NGLOG_DEBUG(HW_GPU, "Uploading GPU macro {:08X}", value);
         current_macro_entry = value;
         current_macro_code.clear();
         return;
@@ -58,7 +60,7 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
 
     if (method == static_cast<u32>(BufferMethods::BindObject)) {
         // Bind the current subchannel to the desired engine id.
-        LOG_DEBUG(HW_GPU, "Binding subchannel %u to engine %u", subchannel, value);
+        NGLOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", subchannel, value);
         ASSERT(bound_engines.find(subchannel) == bound_engines.end());
         bound_engines[subchannel] = static_cast<EngineID>(value);
         return;
@@ -66,7 +68,7 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
 
     if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
         // TODO(Subv): Research and implement these methods.
-        LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
+        NGLOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
         return;
     }
 
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 4e9aed380..2acbb9cd6 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -186,8 +186,8 @@ void Maxwell3D::ProcessQueryGet() {
 }
 
 void Maxwell3D::DrawArrays() {
-    LOG_DEBUG(HW_GPU, "called, topology=%d, count=%d", regs.draw.topology.Value(),
-              regs.vertex_buffer.count);
+    NGLOG_DEBUG(HW_GPU, "called, topology={}, count={}",
+                static_cast<u32>(regs.draw.topology.Value()), regs.vertex_buffer.count);
     ASSERT_MSG(!(regs.index_array.count && regs.vertex_buffer.count), "Both indexed and direct?");
 
     auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index b457b1fbe..9b3542e10 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -116,7 +116,7 @@ RasterizerOpenGL::RasterizerOpenGL() {
 
     glEnable(GL_BLEND);
 
-    LOG_CRITICAL(Render_OpenGL, "Sync fixed function OpenGL state here!");
+    NGLOG_CRITICAL(Render_OpenGL, "Sync fixed function OpenGL state here!");
 }
 
 RasterizerOpenGL::~RasterizerOpenGL() {
@@ -252,8 +252,8 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset) {
             break;
         }
         default:
-            LOG_CRITICAL(HW_GPU, "Unimplemented shader index=%d, enable=%d, offset=0x%08X", index,
-                         shader_config.enable.Value(), shader_config.offset);
+            NGLOG_CRITICAL(HW_GPU, "Unimplemented shader index={}, enable={}, offset={:#010X}",
+                           index, shader_config.enable.Value(), shader_config.offset);
             UNREACHABLE();
         }
 
diff --git a/src/video_core/renderer_opengl/renderer_opengl.cpp b/src/video_core/renderer_opengl/renderer_opengl.cpp
index 5ca9821b7..77d1692f4 100644
--- a/src/video_core/renderer_opengl/renderer_opengl.cpp
+++ b/src/video_core/renderer_opengl/renderer_opengl.cpp
@@ -302,8 +302,8 @@ void RendererOpenGL::DrawScreenTriangles(const ScreenInfo& screen_info, float x,
             right = texcoords.left;
         } else {
             // Other transformations are unsupported
-            LOG_CRITICAL(Render_OpenGL, "Unsupported framebuffer_transform_flags=%d",
-                         framebuffer_transform_flags);
+            NGLOG_CRITICAL(Render_OpenGL, "Unsupported framebuffer_transform_flags={}",
+                           static_cast<u32>(framebuffer_transform_flags));
             UNIMPLEMENTED();
         }
     }
@@ -428,9 +428,9 @@ bool RendererOpenGL::Init() {
     const char* gpu_vendor{reinterpret_cast<char const*>(glGetString(GL_VENDOR))};
     const char* gpu_model{reinterpret_cast<char const*>(glGetString(GL_RENDERER))};
 
-    LOG_INFO(Render_OpenGL, "GL_VERSION: %s", gl_version);
-    LOG_INFO(Render_OpenGL, "GL_VENDOR: %s", gpu_vendor);
-    LOG_INFO(Render_OpenGL, "GL_RENDERER: %s", gpu_model);
+    NGLOG_INFO(Render_OpenGL, "GL_VERSION: {}", gl_version);
+    NGLOG_INFO(Render_OpenGL, "GL_VENDOR: {}", gpu_vendor);
+    NGLOG_INFO(Render_OpenGL, "GL_RENDERER: {}", gpu_model);
 
     Core::Telemetry().AddField(Telemetry::FieldType::UserSystem, "GPU_Vendor", gpu_vendor);
     Core::Telemetry().AddField(Telemetry::FieldType::UserSystem, "GPU_Model", gpu_model);
diff --git a/src/video_core/video_core.cpp b/src/video_core/video_core.cpp
index 289140f31..89dc8ed1e 100644
--- a/src/video_core/video_core.cpp
+++ b/src/video_core/video_core.cpp
@@ -24,9 +24,9 @@ bool Init(EmuWindow* emu_window) {
     g_renderer = std::make_unique<RendererOpenGL>();
     g_renderer->SetWindow(g_emu_window);
     if (g_renderer->Init()) {
-        LOG_DEBUG(Render, "initialized OK");
+        NGLOG_DEBUG(Render, "initialized OK");
     } else {
-        LOG_CRITICAL(Render, "initialization failed !");
+        NGLOG_CRITICAL(Render, "initialization failed !");
         return false;
     }
     return true;
@@ -36,7 +36,7 @@ bool Init(EmuWindow* emu_window) {
 void Shutdown() {
     g_renderer.reset();
 
-    LOG_DEBUG(Render, "shutdown OK");
+    NGLOG_DEBUG(Render, "shutdown OK");
 }
 
 } // namespace VideoCore
-- 
cgit v1.2.3


From a994446b6ec776c9383e8b13c45eeb461405adff Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 23 Apr 2018 20:01:29 -0500
Subject: GPU: Move the Maxwell3D macro uploading code to the inside of the
 Maxwell3D processor.

It doesn't belong in the PFIFO handler.
---
 src/video_core/command_processor.cpp  | 25 -------------------------
 src/video_core/engines/maxwell_3d.cpp | 14 ++++++++++----
 src/video_core/engines/maxwell_3d.h   | 17 +++++++++++++----
 src/video_core/gpu.h                  |  7 -------
 4 files changed, 23 insertions(+), 40 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 26792a2bf..2eaece298 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -24,9 +24,6 @@ namespace Tegra {
 
 enum class BufferMethods {
     BindObject = 0,
-    SetGraphMacroCode = 0x45,
-    SetGraphMacroCodeArg = 0x46,
-    SetGraphMacroEntry = 0x47,
     CountBufferMethods = 0x40,
 };
 
@@ -36,28 +33,6 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
                   "{:08X} remaining params {}",
                   method, subchannel, value, remaining_params);
 
-    if (method == static_cast<u32>(BufferMethods::SetGraphMacroEntry)) {
-        // Prepare to upload a new macro, reset the upload counter.
-        NGLOG_DEBUG(HW_GPU, "Uploading GPU macro {:08X}", value);
-        current_macro_entry = value;
-        current_macro_code.clear();
-        return;
-    }
-
-    if (method == static_cast<u32>(BufferMethods::SetGraphMacroCodeArg)) {
-        // Append a new code word to the current macro.
-        current_macro_code.push_back(value);
-
-        // There are no more params remaining, submit the code to the 3D engine.
-        if (remaining_params == 0) {
-            maxwell_3d->SubmitMacroCode(current_macro_entry, std::move(current_macro_code));
-            current_macro_entry = InvalidGraphMacroEntry;
-            current_macro_code.clear();
-        }
-
-        return;
-    }
-
     if (method == static_cast<u32>(BufferMethods::BindObject)) {
         // Bind the current subchannel to the desired engine id.
         NGLOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", subchannel, value);
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 2acbb9cd6..bc40f8d98 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -22,10 +22,6 @@ constexpr u32 MacroRegistersStart = 0xE00;
 Maxwell3D::Maxwell3D(MemoryManager& memory_manager)
     : memory_manager(memory_manager), macro_interpreter(*this) {}
 
-void Maxwell3D::SubmitMacroCode(u32 entry, std::vector<u32> code) {
-    uploaded_macros[entry * 2 + MacroRegistersStart] = std::move(code);
-}
-
 void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
     auto macro_code = uploaded_macros.find(method);
     // The requested macro must have been uploaded already.
@@ -75,6 +71,10 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
     regs.reg_array[method] = value;
 
     switch (method) {
+    case MAXWELL3D_REG_INDEX(macros.data): {
+        ProcessMacroUpload(value);
+        break;
+    }
     case MAXWELL3D_REG_INDEX(code_address.code_address_high):
     case MAXWELL3D_REG_INDEX(code_address.code_address_low): {
         // Note: For some reason games (like Puyo Puyo Tetris) seem to write 0 to the CODE_ADDRESS
@@ -141,6 +141,12 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
     }
 }
 
+void Maxwell3D::ProcessMacroUpload(u32 data) {
+    // Store the uploaded macro code to interpret them when they're called.
+    auto& macro = uploaded_macros[regs.macros.entry * 2 + MacroRegistersStart];
+    macro.push_back(data);
+}
+
 void Maxwell3D::ProcessQueryGet() {
     GPUVAddr sequence_address = regs.query.QueryAddress();
     // Since the sequence address is given as a GPU VAddr, we have to convert it to an application
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index a022665eb..8edc3cd38 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -322,7 +322,15 @@ public:
 
         union {
             struct {
-                INSERT_PADDING_WORDS(0x200);
+                INSERT_PADDING_WORDS(0x45);
+
+                struct {
+                    INSERT_PADDING_WORDS(1);
+                    u32 data;
+                    u32 entry;
+                } macros;
+
+                INSERT_PADDING_WORDS(0x1B8);
 
                 struct {
                     u32 address_high;
@@ -637,9 +645,6 @@ public:
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value, u32 remaining_params);
 
-    /// Uploads the code for a GPU macro program associated with the specified entry.
-    void SubmitMacroCode(u32 entry, std::vector<u32> code);
-
     /// Returns a list of enabled textures for the specified shader stage.
     std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
 
@@ -670,6 +675,9 @@ private:
      */
     void CallMacroMethod(u32 method, std::vector<u32> parameters);
 
+    /// Handles writes to the macro uploading registers.
+    void ProcessMacroUpload(u32 data);
+
     /// Handles a write to the QUERY_GET register.
     void ProcessQueryGet();
 
@@ -687,6 +695,7 @@ private:
     static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4,                           \
                   "Field " #field_name " has invalid position")
 
+ASSERT_REG_POSITION(macros, 0x45);
 ASSERT_REG_POSITION(rt, 0x200);
 ASSERT_REG_POSITION(viewport_transform[0], 0x280);
 ASSERT_REG_POSITION(viewport, 0x300);
diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h
index 2888daedc..7afa6aaef 100644
--- a/src/video_core/gpu.h
+++ b/src/video_core/gpu.h
@@ -86,8 +86,6 @@ public:
     }
 
 private:
-    static constexpr u32 InvalidGraphMacroEntry = 0xFFFFFFFF;
-
     /// Writes a single register in the engine bound to the specified subchannel
     void WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params);
 
@@ -100,11 +98,6 @@ private:
     std::unique_ptr<Engines::Fermi2D> fermi_2d;
     /// Compute engine
     std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
-
-    /// Entry of the macro that is currently being uploaded
-    u32 current_macro_entry = InvalidGraphMacroEntry;
-    /// Code being uploaded for the current macro
-    std::vector<u32> current_macro_code;
 };
 
 } // namespace Tegra
-- 
cgit v1.2.3


From c16cfbbc6c062491d84a6bc9976027b7a7587fdb Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 23 Apr 2018 20:03:50 -0500
Subject: GPU: Reduce the number of registers of Maxwell3D to 0xE00.

The rest are just macro shim registers.
---
 src/video_core/engines/maxwell_3d.cpp | 6 +++---
 src/video_core/engines/maxwell_3d.h   | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index bc40f8d98..4306b894f 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -33,9 +33,6 @@ void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
 }
 
 void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
-    ASSERT_MSG(method < Regs::NUM_REGS,
-               "Invalid Maxwell3D register, increase the size of the Regs structure");
-
     auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
 
     // It is an error to write to a register other than the current macro's ARG register before it
@@ -64,6 +61,9 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
         return;
     }
 
+    ASSERT_MSG(method < Regs::NUM_REGS,
+               "Invalid Maxwell3D register, increase the size of the Regs structure");
+
     if (debug_context) {
         debug_context->OnEvent(Tegra::DebugContext::Event::MaxwellCommandLoaded, nullptr);
     }
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 8edc3cd38..5cf62fb01 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -31,7 +31,7 @@ public:
     /// Register structure of the Maxwell3D engine.
     /// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
     struct Regs {
-        static constexpr size_t NUM_REGS = 0xE36;
+        static constexpr size_t NUM_REGS = 0xE00;
 
         static constexpr size_t NumRenderTargets = 8;
         static constexpr size_t NumViewports = 16;
@@ -613,7 +613,7 @@ public:
                     u32 size[MaxShaderStage];
                 } tex_info_buffers;
 
-                INSERT_PADDING_WORDS(0x102);
+                INSERT_PADDING_WORDS(0xCC);
             };
             std::array<u32, NUM_REGS> reg_array;
         };
-- 
cgit v1.2.3


From b1109931b9a92ce89635cb7c0c0c1c0c7e6866ed Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 23 Apr 2018 20:12:40 -0500
Subject: GPU: Added boilerplate code for the Fermi2D engine

---
 src/video_core/engines/fermi_2d.cpp |  7 ++++++-
 src/video_core/engines/fermi_2d.h   | 28 +++++++++++++++++++++++++++-
 src/video_core/gpu.cpp              |  2 +-
 3 files changed, 34 insertions(+), 3 deletions(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 7aab163dc..87634da21 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -7,7 +7,12 @@
 namespace Tegra {
 namespace Engines {
 
-void Fermi2D::WriteReg(u32 method, u32 value) {}
+Fermi2D::Fermi2D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
+
+void Fermi2D::WriteReg(u32 method, u32 value) {
+    ASSERT_MSG(method < Regs::NUM_REGS,
+               "Invalid Fermi2D register, increase the size of the Regs structure");
+}
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 8967ddede..a97f5bb28 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -4,19 +4,45 @@
 
 #pragma once
 
+#include <array>
+#include "common/assert.h"
+#include "common/common_funcs.h"
 #include "common/common_types.h"
+#include "video_core/memory_manager.h"
 
 namespace Tegra {
 namespace Engines {
 
+#define FERMI2D_REG_INDEX(field_name)                                                              \
+    (offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
+
 class Fermi2D final {
 public:
-    Fermi2D() = default;
+    explicit Fermi2D(MemoryManager& memory_manager);
     ~Fermi2D() = default;
 
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
+
+    struct Regs {
+        static constexpr size_t NUM_REGS = 0x258;
+
+        union {
+            struct {
+                INSERT_PADDING_WORDS(0x258);
+            };
+            std::array<u32, NUM_REGS> reg_array;
+        };
+    } regs{};
+
+    MemoryManager& memory_manager;
 };
 
+#define ASSERT_REG_POSITION(field_name, position)                                                  \
+    static_assert(offsetof(Fermi2D::Regs, field_name) == position * 4,                             \
+                  "Field " #field_name " has invalid position")
+
+#undef ASSERT_REG_POSITION
+
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/gpu.cpp b/src/video_core/gpu.cpp
index 9463cd5d6..351d21711 100644
--- a/src/video_core/gpu.cpp
+++ b/src/video_core/gpu.cpp
@@ -12,7 +12,7 @@ namespace Tegra {
 GPU::GPU() {
     memory_manager = std::make_unique<MemoryManager>();
     maxwell_3d = std::make_unique<Engines::Maxwell3D>(*memory_manager);
-    fermi_2d = std::make_unique<Engines::Fermi2D>();
+    fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager);
     maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
 }
 
-- 
cgit v1.2.3


From 378c881427d34962461099ef3d55de871710b897 Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 23 Apr 2018 22:14:08 -0500
Subject: GPU: Added surface copy registers to Fermi2D

---
 src/video_core/engines/fermi_2d.h | 58 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index a97f5bb28..78d06218f 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -6,8 +6,10 @@
 
 #include <array>
 #include "common/assert.h"
+#include "common/bit_field.h"
 #include "common/common_funcs.h"
 #include "common/common_types.h"
+#include "video_core/gpu.h"
 #include "video_core/memory_manager.h"
 
 namespace Tegra {
@@ -27,9 +29,59 @@ public:
     struct Regs {
         static constexpr size_t NUM_REGS = 0x258;
 
+        struct Surface {
+            RenderTargetFormat format;
+            BitField<0, 1, u32> linear;
+            union {
+                BitField<0, 4, u32> block_depth;
+                BitField<4, 4, u32> block_height;
+                BitField<8, 4, u32> block_width;
+            };
+            u32 depth;
+            u32 layer;
+            u32 pitch;
+            u32 width;
+            u32 height;
+            u32 address_high;
+            u32 address_low;
+
+            GPUVAddr Address() const {
+                return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
+                                             address_low);
+            }
+        };
+        static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
+
+        enum class Operation : u32 {
+            SrcCopyAnd = 0,
+            ROPAnd = 1,
+            Blend = 2,
+            SrcCopy = 3,
+            ROP = 4,
+            SrcCopyPremult = 5,
+            BlendPremult = 6,
+        };
+
         union {
             struct {
-                INSERT_PADDING_WORDS(0x258);
+                INSERT_PADDING_WORDS(0x80);
+
+                Surface dst;
+
+                INSERT_PADDING_WORDS(2);
+
+                Surface src;
+
+                INSERT_PADDING_WORDS(0x15);
+
+                Operation operation;
+
+                INSERT_PADDING_WORDS(0x9);
+
+                // TODO(Subv): This is only a guess.
+                u32 trigger;
+
+                INSERT_PADDING_WORDS(0x1A3);
             };
             std::array<u32, NUM_REGS> reg_array;
         };
@@ -42,6 +94,10 @@ public:
     static_assert(offsetof(Fermi2D::Regs, field_name) == position * 4,                             \
                   "Field " #field_name " has invalid position")
 
+ASSERT_REG_POSITION(dst, 0x80);
+ASSERT_REG_POSITION(src, 0x8C);
+ASSERT_REG_POSITION(operation, 0xAB);
+ASSERT_REG_POSITION(trigger, 0xB5);
 #undef ASSERT_REG_POSITION
 
 } // namespace Engines
-- 
cgit v1.2.3


From e9ad8e9185a4ab7f29728dbaf131de328eefc4fc Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Wed, 25 Apr 2018 12:52:55 -0500
Subject: Shaders: Added bit decodings for the I2I instruction.

---
 src/video_core/engines/shader_bytecode.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 6cae6ff45..f4d11fa5d 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -275,6 +275,9 @@ public:
         I2F_C,
         I2F_R,
         I2F_IMM,
+        I2I_C,
+        I2I_R,
+        I2I_IMM,
         LOP32I,
         MOV_C,
         MOV_R,
@@ -427,6 +430,9 @@ private:
             INST("0100110010111---", Id::I2F_C, Type::Arithmetic, "I2F_C"),
             INST("0101110010111---", Id::I2F_R, Type::Arithmetic, "I2F_R"),
             INST("0011100-10111---", Id::I2F_IMM, Type::Arithmetic, "I2F_IMM"),
+            INST("0100110011100---", Id::I2I_C, Type::Arithmetic, "I2I_C"),
+            INST("0101110011100---", Id::I2I_R, Type::Arithmetic, "I2I_R"),
+            INST("01110001-1000---", Id::I2I_IMM, Type::Arithmetic, "I2I_IMM"),
             INST("000001----------", Id::LOP32I, Type::Arithmetic, "LOP32I"),
             INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
             INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
-- 
cgit v1.2.3


From 20d86d8a36dca4bf1b465193745a365c3ab9abcd Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Tue, 24 Apr 2018 22:00:40 -0500
Subject: GPU: Partially implemented the Fermi2D surface copy operation.

The hardware allows for some rather complicated operations to be performed on the data during the copy, this is not implemented.
Only same-format same-size raw copies are implemented for now.
---
 src/video_core/engines/fermi_2d.cpp | 54 +++++++++++++++++++++++++++++++++++++
 src/video_core/engines/fermi_2d.h   |  5 ++++
 2 files changed, 59 insertions(+)

(limited to 'src/video_core/engines')

diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 87634da21..9019f2504 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -2,7 +2,9 @@
 // Licensed under GPLv2 or any later version
 // Refer to the license.txt file included.
 
+#include "core/memory.h"
 #include "video_core/engines/fermi_2d.h"
+#include "video_core/textures/decoders.h"
 
 namespace Tegra {
 namespace Engines {
@@ -12,6 +14,58 @@ Fermi2D::Fermi2D(MemoryManager& memory_manager) : memory_manager(memory_manager)
 void Fermi2D::WriteReg(u32 method, u32 value) {
     ASSERT_MSG(method < Regs::NUM_REGS,
                "Invalid Fermi2D register, increase the size of the Regs structure");
+
+    regs.reg_array[method] = value;
+
+    switch (method) {
+    case FERMI2D_REG_INDEX(trigger): {
+        HandleSurfaceCopy();
+        break;
+    }
+    }
+}
+
+void Fermi2D::HandleSurfaceCopy() {
+    NGLOG_WARNING(HW_GPU, "Requested a surface copy with operation {}",
+                  static_cast<u32>(regs.operation));
+
+    const GPUVAddr source = regs.src.Address();
+    const GPUVAddr dest = regs.dst.Address();
+
+    // TODO(Subv): Only same-format and same-size copies are allowed for now.
+    ASSERT(regs.src.format == regs.dst.format);
+    ASSERT(regs.src.width * regs.src.height == regs.dst.width * regs.dst.height);
+
+    // TODO(Subv): Only raw copies are implemented.
+    ASSERT(regs.operation == Regs::Operation::SrcCopy);
+
+    const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
+    const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
+
+    u32 src_bytes_per_pixel = RenderTargetBytesPerPixel(regs.src.format);
+    u32 dst_bytes_per_pixel = RenderTargetBytesPerPixel(regs.dst.format);
+
+    if (regs.src.linear == regs.dst.linear) {
+        // If the input layout and the output layout are the same, just perform a raw copy.
+        Memory::CopyBlock(dest_cpu, source_cpu,
+                          src_bytes_per_pixel * regs.dst.width * regs.dst.height);
+        return;
+    }
+
+    u8* src_buffer = Memory::GetPointer(source_cpu);
+    u8* dst_buffer = Memory::GetPointer(dest_cpu);
+
+    if (!regs.src.linear && regs.dst.linear) {
+        // If the input is tiled and the output is linear, deswizzle the input and copy it over.
+        Texture::CopySwizzledData(regs.src.width, regs.src.height, src_bytes_per_pixel,
+                                  dst_bytes_per_pixel, src_buffer, dst_buffer, true,
+                                  regs.src.block_height);
+    } else {
+        // If the input is linear and the output is tiled, swizzle the input and copy it over.
+        Texture::CopySwizzledData(regs.src.width, regs.src.height, src_bytes_per_pixel,
+                                  dst_bytes_per_pixel, dst_buffer, src_buffer, false,
+                                  regs.dst.block_height);
+    }
 }
 
 } // namespace Engines
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 78d06218f..0c5b413cc 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -88,6 +88,11 @@ public:
     } regs{};
 
     MemoryManager& memory_manager;
+
+private:
+    /// Performs the copy from the source surface to the destination surface as configured in the
+    /// registers.
+    void HandleSurfaceCopy();
 };
 
 #define ASSERT_REG_POSITION(field_name, position)                                                  \
-- 
cgit v1.2.3