From 103b9da4f7115ff47eee52d0dbd31b5b7a18b257 Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Mon, 1 Mar 2021 15:58:16 -0500
Subject: shader: Implement FLO

---
 .../maxwell/translate/impl/find_leading_one.cpp    | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp

(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp')

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
new file mode 100644
index 000000000..d5361bec5
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
@@ -0,0 +1,46 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/bit_field.h"
+#include "common/common_types.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+namespace {
+void FLO(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
+    union {
+        u64 insn;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<40, 1, u64> tilde;
+        BitField<41, 1, u64> shift;
+        BitField<48, 1, u64> is_signed;
+    } const flo{insn};
+
+    const bool invert{flo.tilde != 0};
+    const bool is_signed{flo.is_signed != 0};
+    const bool shift_op{flo.shift != 0};
+
+    const IR::U32 operand{invert ? v.ir.BitwiseNot(src) : src};
+    const IR::U32 find_result{is_signed ? v.ir.FindSMsb(operand) : v.ir.FindUMsb(operand)};
+    const IR::U1 find_fail{v.ir.IEqual(find_result, v.ir.Imm32(-1))};
+    const IR::U32 offset{v.ir.Imm32(31)};
+    const IR::U32 success_result{shift_op ? IR::U32{v.ir.ISub(offset, find_result)} : find_result};
+
+    const IR::U32 result{v.ir.Select(find_fail, find_result, success_result)};
+    v.X(flo.dest_reg, result);
+}
+} // Anonymous namespace
+
+void TranslatorVisitor::FLO_reg(u64 insn) {
+    FLO(*this, insn, GetReg20(insn));
+}
+
+void TranslatorVisitor::FLO_cbuf(u64 insn) {
+    FLO(*this, insn, GetCbuf(insn));
+}
+
+void TranslatorVisitor::FLO_imm(u64 insn) {
+    FLO(*this, insn, GetImm20(insn));
+}
+} // namespace Shader::Maxwell
-- 
cgit v1.2.3


From 415c7e46ed2f00bb4611cf2913eac1b92ca130bc Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Sun, 11 Apr 2021 20:54:51 -0300
Subject: shader: Simplify FLO and throw on CC

---
 .../maxwell/translate/impl/find_leading_one.cpp    | 25 +++++++++++-----------
 1 file changed, 13 insertions(+), 12 deletions(-)

(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp')

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
index d5361bec5..f0cb25d61 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
@@ -8,26 +8,27 @@
 
 namespace Shader::Maxwell {
 namespace {
-void FLO(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
+void FLO(TranslatorVisitor& v, u64 insn, IR::U32 src) {
     union {
         u64 insn;
         BitField<0, 8, IR::Reg> dest_reg;
         BitField<40, 1, u64> tilde;
         BitField<41, 1, u64> shift;
+        BitField<47, 1, u64> cc;
         BitField<48, 1, u64> is_signed;
     } const flo{insn};
 
-    const bool invert{flo.tilde != 0};
-    const bool is_signed{flo.is_signed != 0};
-    const bool shift_op{flo.shift != 0};
-
-    const IR::U32 operand{invert ? v.ir.BitwiseNot(src) : src};
-    const IR::U32 find_result{is_signed ? v.ir.FindSMsb(operand) : v.ir.FindUMsb(operand)};
-    const IR::U1 find_fail{v.ir.IEqual(find_result, v.ir.Imm32(-1))};
-    const IR::U32 offset{v.ir.Imm32(31)};
-    const IR::U32 success_result{shift_op ? IR::U32{v.ir.ISub(offset, find_result)} : find_result};
-
-    const IR::U32 result{v.ir.Select(find_fail, find_result, success_result)};
+    if (flo.cc != 0) {
+        throw NotImplementedException("CC");
+    }
+    if (flo.tilde != 0) {
+        src = v.ir.BitwiseNot(src);
+    }
+    IR::U32 result{flo.is_signed != 0 ? v.ir.FindSMsb(src) : v.ir.FindUMsb(src)};
+    if (flo.shift != 0) {
+        const IR::U1 not_found{v.ir.IEqual(result, v.ir.Imm32(-1))};
+        result = IR::U32{v.ir.Select(not_found, result, v.ir.BitwiseXor(result, v.ir.Imm32(31)))};
+    }
     v.X(flo.dest_reg, result);
 }
 } // Anonymous namespace
-- 
cgit v1.2.3