From e628ed481079d26cad4980f5094dbca16bae96c8 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 6 Apr 2015 09:12:55 -0400 Subject: dyncom: Set CP15 reset values on initialization --- src/core/arm/interpreter/arminit.cpp | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'src/core/arm/interpreter/arminit.cpp') diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 4ac827e0a..710115375 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -66,6 +66,64 @@ void ARMul_SelectProcessor(ARMul_State* state, unsigned properties) ARMul_CoProInit(state); } +// Resets certain MPCore CP15 values to their ARM-defined reset values. +static void ResetMPCoreCP15Registers(ARMul_State* cpu) +{ + // c0 + cpu->CP15[CP15(CP15_MAIN_ID)] = 0x410FB024; + cpu->CP15[CP15(CP15_TLB_TYPE)] = 0x00000800; + cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)] = 0x00000111; + cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)] = 0x00000001; + cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)] = 0x00000002; + cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)] = 0x01100103; + cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)] = 0x10020302; + cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)] = 0x01222000; + cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)] = 0x00000000; + cpu->CP15[CP15(CP15_ISA_FEATURE_0)] = 0x00100011; + cpu->CP15[CP15(CP15_ISA_FEATURE_1)] = 0x12002111; + cpu->CP15[CP15(CP15_ISA_FEATURE_2)] = 0x11221011; + cpu->CP15[CP15(CP15_ISA_FEATURE_3)] = 0x01102131; + cpu->CP15[CP15(CP15_ISA_FEATURE_4)] = 0x00000141; + + // c1 + cpu->CP15[CP15(CP15_CONTROL)] = 0x00054078; + cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = 0x0000000F; + cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = 0x00000000; + + // c2 + cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = 0x00000000; + cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = 0x00000000; + cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = 0x00000000; + + // c3 + cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = 0x00000000; + + // c7 + cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = 0x00000000; + + // c9 + cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = 0xFFFFFFF0; + + // c10 + cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = 0x00000000; + cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = 0x00098AA4; + cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = 0x44E048E0; + + // c13 + cpu->CP15[CP15(CP15_PID)] = 0x00000000; + cpu->CP15[CP15(CP15_CONTEXT_ID)] = 0x00000000; + cpu->CP15[CP15(CP15_THREAD_UPRW)] = 0x00000000; + cpu->CP15[CP15(CP15_THREAD_URO)] = 0x00000000; + cpu->CP15[CP15(CP15_THREAD_PRW)] = 0x00000000; + + // c15 + cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = 0x00000000; + cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = 0x00000000; + cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = 0x00000000; + cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = 0x00000000; + cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = 0x00000000; +} + /***************************************************************************\ * Call this routine to set up the initial machine state (or perform a RESET * \***************************************************************************/ @@ -80,6 +138,8 @@ void ARMul_Reset(ARMul_State* state) state->Bank = SVCBANK; FLUSHPIPE; + ResetMPCoreCP15Registers(state); + state->EndCondition = 0; state->ErrorCode = 0; -- cgit v1.2.3 From 23dd2ca8a6757d356cbc7954a431bfc227ec6d9a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 6 Apr 2015 09:25:11 -0400 Subject: dyncom: Properly return the value of the user RO thread register --- src/core/arm/interpreter/arminit.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/core/arm/interpreter/arminit.cpp') diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 710115375..c6b8197f6 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -16,6 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include +#include "core/mem_map.h" #include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armemu.h" @@ -138,8 +139,16 @@ void ARMul_Reset(ARMul_State* state) state->Bank = SVCBANK; FLUSHPIPE; + // Reset CP15 ResetMPCoreCP15Registers(state); + // This is separate from the CP15 register reset function, as + // this isn't an ARM-defined reset value; it's set by the 3DS. + // + // TODO: Whenever TLS is implemented, this should contain + // the address of the 0x200-byte TLS + state->CP15[CP15(CP15_THREAD_URO)] = Memory::KERNEL_MEMORY_VADDR; + state->EndCondition = 0; state->ErrorCode = 0; -- cgit v1.2.3 From b7b8b676202eaeced392dea06e2c3fcc4bd11aec Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 6 Apr 2015 12:43:23 -0400 Subject: Move CP15 enum definitions into their own enum. Also gets rid of preprocessor mumbo-jumbo --- src/core/arm/interpreter/arminit.cpp | 74 ++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 37 deletions(-) (limited to 'src/core/arm/interpreter/arminit.cpp') diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index c6b8197f6..7254a16f3 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -71,58 +71,58 @@ void ARMul_SelectProcessor(ARMul_State* state, unsigned properties) static void ResetMPCoreCP15Registers(ARMul_State* cpu) { // c0 - cpu->CP15[CP15(CP15_MAIN_ID)] = 0x410FB024; - cpu->CP15[CP15(CP15_TLB_TYPE)] = 0x00000800; - cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)] = 0x00000111; - cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)] = 0x00000001; - cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)] = 0x00000002; - cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)] = 0x01100103; - cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)] = 0x10020302; - cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)] = 0x01222000; - cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)] = 0x00000000; - cpu->CP15[CP15(CP15_ISA_FEATURE_0)] = 0x00100011; - cpu->CP15[CP15(CP15_ISA_FEATURE_1)] = 0x12002111; - cpu->CP15[CP15(CP15_ISA_FEATURE_2)] = 0x11221011; - cpu->CP15[CP15(CP15_ISA_FEATURE_3)] = 0x01102131; - cpu->CP15[CP15(CP15_ISA_FEATURE_4)] = 0x00000141; + cpu->CP15[CP15_MAIN_ID] = 0x410FB024; + cpu->CP15[CP15_TLB_TYPE] = 0x00000800; + cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111; + cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001; + cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000; + cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011; + cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111; + cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011; + cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131; + cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141; // c1 - cpu->CP15[CP15(CP15_CONTROL)] = 0x00054078; - cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = 0x0000000F; - cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = 0x00000000; + cpu->CP15[CP15_CONTROL] = 0x00054078; + cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F; + cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000; // c2 - cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = 0x00000000; - cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = 0x00000000; - cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = 0x00000000; + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000; + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000; + cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000; // c3 - cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = 0x00000000; + cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000; // c7 - cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = 0x00000000; + cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000; // c9 - cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = 0xFFFFFFF0; + cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0; // c10 - cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = 0x00000000; - cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = 0x00098AA4; - cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = 0x44E048E0; + cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000; + cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4; + cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0; // c13 - cpu->CP15[CP15(CP15_PID)] = 0x00000000; - cpu->CP15[CP15(CP15_CONTEXT_ID)] = 0x00000000; - cpu->CP15[CP15(CP15_THREAD_UPRW)] = 0x00000000; - cpu->CP15[CP15(CP15_THREAD_URO)] = 0x00000000; - cpu->CP15[CP15(CP15_THREAD_PRW)] = 0x00000000; + cpu->CP15[CP15_PID] = 0x00000000; + cpu->CP15[CP15_CONTEXT_ID] = 0x00000000; + cpu->CP15[CP15_THREAD_UPRW] = 0x00000000; + cpu->CP15[CP15_THREAD_URO] = 0x00000000; + cpu->CP15[CP15_THREAD_PRW] = 0x00000000; // c15 - cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = 0x00000000; - cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = 0x00000000; - cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = 0x00000000; - cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = 0x00000000; - cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = 0x00000000; + cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000; + cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000; } /***************************************************************************\ @@ -147,7 +147,7 @@ void ARMul_Reset(ARMul_State* state) // // TODO: Whenever TLS is implemented, this should contain // the address of the 0x200-byte TLS - state->CP15[CP15(CP15_THREAD_URO)] = Memory::KERNEL_MEMORY_VADDR; + state->CP15[CP15_THREAD_URO] = Memory::KERNEL_MEMORY_VADDR; state->EndCondition = 0; state->ErrorCode = 0; -- cgit v1.2.3 From 8004d35ea163b621ea3f3d4333f2c58ec926d7c9 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Mon, 6 Apr 2015 13:01:19 -0400 Subject: core: Migrate 3DS-specific CP15 register setting into Init --- src/core/arm/interpreter/arminit.cpp | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/core/arm/interpreter/arminit.cpp') diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 7254a16f3..1d732fe84 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -139,16 +139,8 @@ void ARMul_Reset(ARMul_State* state) state->Bank = SVCBANK; FLUSHPIPE; - // Reset CP15 ResetMPCoreCP15Registers(state); - // This is separate from the CP15 register reset function, as - // this isn't an ARM-defined reset value; it's set by the 3DS. - // - // TODO: Whenever TLS is implemented, this should contain - // the address of the 0x200-byte TLS - state->CP15[CP15_THREAD_URO] = Memory::KERNEL_MEMORY_VADDR; - state->EndCondition = 0; state->ErrorCode = 0; -- cgit v1.2.3