diff options
Diffstat (limited to 'src/video_core')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 12 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_compute.cpp | 19 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_compute.h | 36 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_rasterizer.cpp | 22 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_rasterizer.h | 6 | ||||
| -rw-r--r-- | src/video_core/textures/decoders.cpp | 117 |
6 files changed, 158 insertions, 54 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index b81b0723d..16cdfc7e2 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -461,7 +461,11 @@ public: u32 entry; } macros; - INSERT_PADDING_WORDS(0x1B8); + INSERT_PADDING_WORDS(0x189); + + u32 tfb_enabled; + + INSERT_PADDING_WORDS(0x2E); RenderTargetConfig rt[NumRenderTargets]; @@ -594,7 +598,9 @@ public: u32 depth_write_enabled; - INSERT_PADDING_WORDS(0x7); + u32 alpha_test_enabled; + + INSERT_PADDING_WORDS(0x6); u32 d3d_cull_mode; @@ -977,6 +983,7 @@ private: "Field " #field_name " has invalid position") ASSERT_REG_POSITION(macros, 0x45); +ASSERT_REG_POSITION(tfb_enabled, 0x1D1); ASSERT_REG_POSITION(rt, 0x200); ASSERT_REG_POSITION(viewport_transform[0], 0x280); ASSERT_REG_POSITION(viewport, 0x300); @@ -996,6 +1003,7 @@ ASSERT_REG_POSITION(zeta_height, 0x48b); ASSERT_REG_POSITION(depth_test_enable, 0x4B3); ASSERT_REG_POSITION(independent_blend_enable, 0x4B9); ASSERT_REG_POSITION(depth_write_enabled, 0x4BA); +ASSERT_REG_POSITION(alpha_test_enabled, 0x4BB); ASSERT_REG_POSITION(d3d_cull_mode, 0x4C2); ASSERT_REG_POSITION(depth_test_func, 0x4C3); ASSERT_REG_POSITION(blend, 0x4CF); diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp index e4e5f9e5e..59e28b22d 100644 --- a/src/video_core/engines/maxwell_compute.cpp +++ b/src/video_core/engines/maxwell_compute.cpp @@ -2,12 +2,29 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. +#include "common/logging/log.h" +#include "core/core.h" #include "video_core/engines/maxwell_compute.h" namespace Tegra { namespace Engines { -void MaxwellCompute::WriteReg(u32 method, u32 value) {} +void MaxwellCompute::WriteReg(u32 method, u32 value) { + ASSERT_MSG(method < Regs::NUM_REGS, + "Invalid MaxwellCompute register, increase the size of the Regs structure"); + + regs.reg_array[method] = value; + + switch (method) { + case MAXWELL_COMPUTE_REG_INDEX(compute): { + LOG_CRITICAL(HW_GPU, "Compute shaders are not implemented"); + UNREACHABLE(); + break; + } + default: + break; + } +} } // namespace Engines } // namespace Tegra diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h index 2b3e4ced6..6ea934fb9 100644 --- a/src/video_core/engines/maxwell_compute.h +++ b/src/video_core/engines/maxwell_compute.h @@ -4,17 +4,53 @@ #pragma once +#include <array> +#include "common/assert.h" +#include "common/bit_field.h" +#include "common/common_funcs.h" #include "common/common_types.h" namespace Tegra::Engines { +#define MAXWELL_COMPUTE_REG_INDEX(field_name) \ + (offsetof(Tegra::Engines::MaxwellCompute::Regs, field_name) / sizeof(u32)) + class MaxwellCompute final { public: MaxwellCompute() = default; ~MaxwellCompute() = default; + struct Regs { + static constexpr std::size_t NUM_REGS = 0xCF8; + + union { + struct { + INSERT_PADDING_WORDS(0x281); + + union { + u32 compute_end; + BitField<0, 1, u32> unknown; + } compute; + + INSERT_PADDING_WORDS(0xA76); + }; + std::array<u32, NUM_REGS> reg_array; + }; + } regs{}; + + static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), + "MaxwellCompute Regs has wrong size"); + /// Write the value to the register identified by method. void WriteReg(u32 method, u32 value); }; +#define ASSERT_REG_POSITION(field_name, position) \ + static_assert(offsetof(MaxwellCompute::Regs, field_name) == position * 4, \ + "Field " #field_name " has invalid position") + +ASSERT_REG_POSITION(compute, 0x281); + +#undef ASSERT_REG_POSITION + } // namespace Tegra::Engines diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp index 70fb54507..44850d193 100644 --- a/src/video_core/renderer_opengl/gl_rasterizer.cpp +++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp @@ -450,6 +450,8 @@ void RasterizerOpenGL::DrawArrays() { SyncBlendState(); SyncLogicOpState(); SyncCullMode(); + SyncAlphaTest(); + SyncTransformFeedback(); // TODO(bunnei): Sync framebuffer_scale uniform here // TODO(bunnei): Sync scissorbox uniform(s) here @@ -883,4 +885,24 @@ void RasterizerOpenGL::SyncLogicOpState() { state.logic_op.operation = MaxwellToGL::LogicOp(regs.logic_op.operation); } +void RasterizerOpenGL::SyncAlphaTest() { + const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs; + + // TODO(Rodrigo): Alpha testing is a legacy OpenGL feature, but it can be + // implemented with a test+discard in fragment shaders. + if (regs.alpha_test_enabled != 0) { + LOG_CRITICAL(Render_OpenGL, "Alpha testing is not implemented"); + UNREACHABLE(); + } +} + +void RasterizerOpenGL::SyncTransformFeedback() { + const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs; + + if (regs.tfb_enabled != 0) { + LOG_CRITICAL(Render_OpenGL, "Transform feedbacks are not implemented"); + UNREACHABLE(); + } +} + } // namespace OpenGL diff --git a/src/video_core/renderer_opengl/gl_rasterizer.h b/src/video_core/renderer_opengl/gl_rasterizer.h index bf9560bdc..c3f1e14bf 100644 --- a/src/video_core/renderer_opengl/gl_rasterizer.h +++ b/src/video_core/renderer_opengl/gl_rasterizer.h @@ -158,6 +158,12 @@ private: /// Syncs the LogicOp state to match the guest state void SyncLogicOpState(); + /// Syncs the alpha test state to match the guest state + void SyncAlphaTest(); + + /// Syncs the transform feedback state to match the guest state + void SyncTransformFeedback(); + bool has_ARB_direct_state_access = false; bool has_ARB_multi_bind = false; bool has_ARB_separate_shader_objects = false; diff --git a/src/video_core/textures/decoders.cpp b/src/video_core/textures/decoders.cpp index 20ba6d4f6..3d5476e5d 100644 --- a/src/video_core/textures/decoders.cpp +++ b/src/video_core/textures/decoders.cpp @@ -13,47 +13,20 @@ namespace Tegra::Texture { /** + * This table represents the internal swizzle of a gob, + * in format 16 bytes x 2 sector packing. * Calculates the offset of an (x, y) position within a swizzled texture. - * Taken from the Tegra X1 TRM. + * Taken from the Tegra X1 Technical Reference Manual. pages 1187-1188 */ -static u32 GetSwizzleOffset(u32 x, u32 y, u32 image_width, u32 bytes_per_pixel, u32 block_height) { - // Round up to the next gob - const u32 image_width_in_gobs{(image_width * bytes_per_pixel + 63) / 64}; - - u32 GOB_address = 0 + (y / (8 * block_height)) * 512 * block_height * image_width_in_gobs + - (x * bytes_per_pixel / 64) * 512 * block_height + - (y % (8 * block_height) / 8) * 512; - x *= bytes_per_pixel; - u32 address = GOB_address + ((x % 64) / 32) * 256 + ((y % 8) / 2) * 64 + ((x % 32) / 16) * 32 + - (y % 2) * 16 + (x % 16); - - return address; -} - -void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel, - u8* swizzled_data, u8* unswizzled_data, bool unswizzle, u32 block_height) { - u8* data_ptrs[2]; - for (unsigned y = 0; y < height; ++y) { - for (unsigned x = 0; x < width; ++x) { - u32 swizzle_offset = GetSwizzleOffset(x, y, width, bytes_per_pixel, block_height); - u32 pixel_index = (x + y * width) * out_bytes_per_pixel; - - data_ptrs[unswizzle] = swizzled_data + swizzle_offset; - data_ptrs[!unswizzle] = &unswizzled_data[pixel_index]; - - std::memcpy(data_ptrs[0], data_ptrs[1], bytes_per_pixel); - } - } -} - -template <std::size_t N, std::size_t M> +template <std::size_t N, std::size_t M, u32 Align> struct alignas(64) SwizzleTable { + static_assert(M * Align == 64, "Swizzle Table does not align to GOB"); constexpr SwizzleTable() { for (u32 y = 0; y < N; ++y) { for (u32 x = 0; x < M; ++x) { - const u32 x2 = x * 16; + const u32 x2 = x * Align; values[y][x] = static_cast<u16>(((x2 % 64) / 32) * 256 + ((y % 8) / 2) * 64 + - ((x2 % 32) / 16) * 32 + (y % 2) * 16); + ((x2 % 32) / 16) * 32 + (y % 2) * 16 + (x2 % 16)); } } } @@ -63,24 +36,60 @@ struct alignas(64) SwizzleTable { std::array<std::array<u16, M>, N> values{}; }; -constexpr auto swizzle_table = SwizzleTable<8, 4>(); +constexpr auto legacy_swizzle_table = SwizzleTable<8, 64, 1>(); +constexpr auto fast_swizzle_table = SwizzleTable<8, 4, 16>(); -void FastSwizzleData(u32 width, u32 height, u32 bytes_per_pixel, u8* swizzled_data, - u8* unswizzled_data, bool unswizzle, u32 block_height) { +static void LegacySwizzleData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel, + u8* swizzled_data, u8* unswizzled_data, bool unswizzle, + u32 block_height) { + std::array<u8*, 2> data_ptrs; + const std::size_t stride = width * bytes_per_pixel; + const std::size_t gobs_in_x = 64; + const std::size_t gobs_in_y = 8; + const std::size_t gobs_size = gobs_in_x * gobs_in_y; + const std::size_t image_width_in_gobs{(stride + gobs_in_x - 1) / gobs_in_x}; + for (std::size_t y = 0; y < height; ++y) { + const std::size_t gob_y_address = + (y / (gobs_in_y * block_height)) * gobs_size * block_height * image_width_in_gobs + + (y % (gobs_in_y * block_height) / gobs_in_y) * gobs_size; + const auto& table = legacy_swizzle_table[y % gobs_in_y]; + for (std::size_t x = 0; x < width; ++x) { + const std::size_t gob_address = + gob_y_address + (x * bytes_per_pixel / gobs_in_x) * gobs_size * block_height; + const std::size_t x2 = x * bytes_per_pixel; + const std::size_t swizzle_offset = gob_address + table[x2 % gobs_in_x]; + const std::size_t pixel_index = (x + y * width) * out_bytes_per_pixel; + + data_ptrs[unswizzle] = swizzled_data + swizzle_offset; + data_ptrs[!unswizzle] = unswizzled_data + pixel_index; + + std::memcpy(data_ptrs[0], data_ptrs[1], bytes_per_pixel); + } + } +} + +static void FastSwizzleData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel, + u8* swizzled_data, u8* unswizzled_data, bool unswizzle, + u32 block_height) { std::array<u8*, 2> data_ptrs; const std::size_t stride{width * bytes_per_pixel}; - const std::size_t image_width_in_gobs{(stride + 63) / 64}; + const std::size_t gobs_in_x = 64; + const std::size_t gobs_in_y = 8; + const std::size_t gobs_size = gobs_in_x * gobs_in_y; + const std::size_t image_width_in_gobs{(stride + gobs_in_x - 1) / gobs_in_x}; const std::size_t copy_size{16}; for (std::size_t y = 0; y < height; ++y) { const std::size_t initial_gob = - (y / (8 * block_height)) * 512 * block_height * image_width_in_gobs + - (y % (8 * block_height) / 8) * 512; - const std::size_t pixel_base{y * width * bytes_per_pixel}; - const auto& table = swizzle_table[y % 8]; + (y / (gobs_in_y * block_height)) * gobs_size * block_height * image_width_in_gobs + + (y % (gobs_in_y * block_height) / gobs_in_y) * gobs_size; + const std::size_t pixel_base{y * width * out_bytes_per_pixel}; + const auto& table = fast_swizzle_table[y % gobs_in_y]; for (std::size_t xb = 0; xb < stride; xb += copy_size) { - const std::size_t gob_address{initial_gob + (xb / 64) * 512 * block_height}; + const std::size_t gob_address{initial_gob + + (xb / gobs_in_x) * gobs_size * block_height}; const std::size_t swizzle_offset{gob_address + table[(xb / 16) % 4]}; - const std::size_t pixel_index{xb + pixel_base}; + const std::size_t out_x = xb * out_bytes_per_pixel / bytes_per_pixel; + const std::size_t pixel_index{out_x + pixel_base}; data_ptrs[unswizzle] = swizzled_data + swizzle_offset; data_ptrs[!unswizzle] = unswizzled_data + pixel_index; std::memcpy(data_ptrs[0], data_ptrs[1], copy_size); @@ -88,6 +97,17 @@ void FastSwizzleData(u32 width, u32 height, u32 bytes_per_pixel, u8* swizzled_da } } +void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel, + u8* swizzled_data, u8* unswizzled_data, bool unswizzle, u32 block_height) { + if (bytes_per_pixel % 3 != 0 && (width * bytes_per_pixel) % 16 == 0) { + FastSwizzleData(width, height, bytes_per_pixel, out_bytes_per_pixel, swizzled_data, + unswizzled_data, unswizzle, block_height); + } else { + LegacySwizzleData(width, height, bytes_per_pixel, out_bytes_per_pixel, swizzled_data, + unswizzled_data, unswizzle, block_height); + } +} + u32 BytesPerPixel(TextureFormat format) { switch (format) { case TextureFormat::DXT1: @@ -134,13 +154,8 @@ u32 BytesPerPixel(TextureFormat format) { std::vector<u8> UnswizzleTexture(VAddr address, u32 tile_size, u32 bytes_per_pixel, u32 width, u32 height, u32 block_height) { std::vector<u8> unswizzled_data(width * height * bytes_per_pixel); - if (bytes_per_pixel % 3 != 0 && (width * bytes_per_pixel) % 16 == 0) { - FastSwizzleData(width / tile_size, height / tile_size, bytes_per_pixel, - Memory::GetPointer(address), unswizzled_data.data(), true, block_height); - } else { - CopySwizzledData(width / tile_size, height / tile_size, bytes_per_pixel, bytes_per_pixel, - Memory::GetPointer(address), unswizzled_data.data(), true, block_height); - } + CopySwizzledData(width / tile_size, height / tile_size, bytes_per_pixel, bytes_per_pixel, + Memory::GetPointer(address), unswizzled_data.data(), true, block_height); return unswizzled_data; } |
