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-rw-r--r--src/video_core/engines/maxwell_3d.cpp5
-rw-r--r--src/video_core/engines/shader_bytecode.h15
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp29
3 files changed, 41 insertions, 8 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 68ff1e86b..e63ad4d46 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -5,6 +5,7 @@
#include <cinttypes>
#include "common/assert.h"
#include "core/core.h"
+#include "core/core_timing.h"
#include "core/memory.h"
#include "video_core/debug_utils/debug_utils.h"
#include "video_core/engines/maxwell_3d.h"
@@ -194,8 +195,8 @@ void Maxwell3D::ProcessQueryGet() {
// wait queues.
LongQueryResult query_result{};
query_result.value = result;
- // TODO(Subv): Generate a real GPU timestamp and write it here instead of 0
- query_result.timestamp = 0;
+ // TODO(Subv): Generate a real GPU timestamp and write it here instead of CoreTiming
+ query_result.timestamp = CoreTiming::GetTicks();
Memory::WriteBlock(*address, &query_result, sizeof(query_result));
}
break;
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 3e4efbe0c..a7daea766 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -243,7 +243,8 @@ enum class TextureType : u64 {
TextureCube = 3,
};
-enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 };
+enum class IpaInterpMode : u64 { Linear = 0, Perspective = 1, Flat = 2, Sc = 3 };
+enum class IpaSampleMode : u64 { Default = 0, Centroid = 1, Offset = 2 };
union Instruction {
Instruction& operator=(const Instruction& instr) {
@@ -328,10 +329,16 @@ union Instruction {
} alu;
union {
- BitField<54, 3, IpaMode> mode;
+ BitField<51, 1, u64> saturate;
+ BitField<52, 2, IpaSampleMode> sample_mode;
+ BitField<54, 2, IpaInterpMode> interp_mode;
} ipa;
union {
+ BitField<39, 2, u64> tab5cb8_2;
+ BitField<41, 3, u64> tab5c68_1;
+ BitField<44, 2, u64> tab5c68_0;
+ BitField<47, 1, u64> cc;
BitField<48, 1, u64> negate_b;
} fmul;
@@ -399,8 +406,11 @@ union Instruction {
} flow;
union {
+ BitField<47, 1, u64> cc;
BitField<48, 1, u64> negate_b;
BitField<49, 1, u64> negate_c;
+ BitField<51, 2, u64> tab5980_1;
+ BitField<53, 2, u64> tab5980_0;
} ffma;
union {
@@ -509,6 +519,7 @@ union Instruction {
union {
BitField<0, 8, Register> gpr0;
BitField<28, 8, Register> gpr28;
+ BitField<49, 1, u64> nodep;
BitField<50, 3, u64> component_mask_selector;
BitField<53, 4, u64> texture_info;
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 391c92d47..c4e7e1e3b 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -887,6 +887,8 @@ private:
// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
+ ASSERT_MSG(instr.texs.nodep == 0, "TEXS nodep not implemented");
+
size_t written_components = 0;
for (u32 component = 0; component < 4; ++component) {
if (!instr.texs.IsComponentEnabled(component)) {
@@ -1038,6 +1040,15 @@ private:
case OpCode::Id::FMUL_R:
case OpCode::Id::FMUL_IMM: {
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
+ ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented",
+ instr.fmul.tab5cb8_2.Value());
+ ASSERT_MSG(instr.fmul.tab5c68_1 == 0, "FMUL tab5cb8_1({}) is not implemented",
+ instr.fmul.tab5c68_1.Value());
+ ASSERT_MSG(instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented",
+ instr.fmul.tab5c68_0
+ .Value()); // SMO typical sends 1 here which seems to be the default
+ ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented");
+
op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
instr.alu.saturate_d);
@@ -1436,6 +1447,12 @@ private:
std::string op_b = instr.ffma.negate_b ? "-" : "";
std::string op_c = instr.ffma.negate_c ? "-" : "";
+ ASSERT_MSG(instr.ffma.cc == 0, "FFMA cc not implemented");
+ ASSERT_MSG(instr.ffma.tab5980_0 == 1, "FFMA tab5980_0({}) not implemented",
+ instr.ffma.tab5980_0.Value()); // Seems to be 1 by default based on SMO
+ ASSERT_MSG(instr.ffma.tab5980_1 == 0, "FFMA tab5980_1({}) not implemented",
+ instr.ffma.tab5980_1.Value());
+
switch (opcode->GetId()) {
case OpCode::Id::FFMA_CR: {
op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
@@ -2110,8 +2127,12 @@ private:
case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28;
const auto& reg = instr.gpr0;
- switch (instr.ipa.mode) {
- case Tegra::Shader::IpaMode::Pass:
+ ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default,
+ "Unhandled IPA sample mode: {}",
+ static_cast<u32>(instr.ipa.sample_mode.Value()));
+ ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented");
+ switch (instr.ipa.interp_mode) {
+ case Tegra::Shader::IpaInterpMode::Linear:
if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
attribute.index == Attribute::Index::Position) {
switch (attribute.element) {
@@ -2132,12 +2153,12 @@ private:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
}
break;
- case Tegra::Shader::IpaMode::None:
+ case Tegra::Shader::IpaInterpMode::Perspective:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
break;
default:
LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
- static_cast<u32>(instr.ipa.mode.Value()));
+ static_cast<u32>(instr.ipa.interp_mode.Value()));
UNREACHABLE();
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-27 08:51:45 +0000