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-rw-r--r--src/video_core/engines/fermi_2d.cpp14
-rw-r--r--src/video_core/engines/fermi_2d.h14
-rw-r--r--src/video_core/engines/maxwell_3d.h24
-rw-r--r--src/video_core/engines/maxwell_dma.cpp10
-rw-r--r--src/video_core/engines/maxwell_dma.h4
-rw-r--r--src/video_core/engines/shader_bytecode.h38
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.cpp3
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer_cache.cpp90
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer_cache.h29
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp90
-rw-r--r--src/video_core/textures/decoders.cpp209
-rw-r--r--src/video_core/textures/decoders.h21
-rw-r--r--src/video_core/textures/texture.h18
13 files changed, 430 insertions, 134 deletions
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 912e785b9..597b279b9 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -62,14 +62,16 @@ void Fermi2D::HandleSurfaceCopy() {
u8* dst_buffer = Memory::GetPointer(dest_cpu);
if (!regs.src.linear && regs.dst.linear) {
// If the input is tiled and the output is linear, deswizzle the input and copy it over.
- Texture::CopySwizzledData(regs.src.width, regs.src.height, src_bytes_per_pixel,
- dst_bytes_per_pixel, src_buffer, dst_buffer, true,
- regs.src.BlockHeight());
+ Texture::CopySwizzledData(regs.src.width, regs.src.height, regs.src.depth,
+ src_bytes_per_pixel, dst_bytes_per_pixel, src_buffer,
+ dst_buffer, true, regs.src.BlockHeight(),
+ regs.src.BlockDepth());
} else {
// If the input is linear and the output is tiled, swizzle the input and copy it over.
- Texture::CopySwizzledData(regs.src.width, regs.src.height, src_bytes_per_pixel,
- dst_bytes_per_pixel, dst_buffer, src_buffer, false,
- regs.dst.BlockHeight());
+ Texture::CopySwizzledData(regs.src.width, regs.src.height, regs.src.depth,
+ src_bytes_per_pixel, dst_bytes_per_pixel, dst_buffer,
+ src_buffer, false, regs.dst.BlockHeight(),
+ regs.dst.BlockDepth());
}
}
}
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 81d15c62a..2a6e8bbbb 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -36,9 +36,9 @@ public:
RenderTargetFormat format;
BitField<0, 1, u32> linear;
union {
- BitField<0, 4, u32> block_depth;
+ BitField<0, 4, u32> block_width;
BitField<4, 4, u32> block_height;
- BitField<8, 4, u32> block_width;
+ BitField<8, 4, u32> block_depth;
};
u32 depth;
u32 layer;
@@ -53,10 +53,20 @@ public:
address_low);
}
+ u32 BlockWidth() const {
+ // The block width is stored in log2 format.
+ return 1 << block_width;
+ }
+
u32 BlockHeight() const {
// The block height is stored in log2 format.
return 1 << block_height;
}
+
+ u32 BlockDepth() const {
+ // The block depth is stored in log2 format.
+ return 1 << block_depth;
+ }
};
static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 20e1884da..c8d1b6478 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -347,6 +347,16 @@ public:
DecrWrap = 8,
};
+ enum class MemoryLayout : u32 {
+ Linear = 0,
+ BlockLinear = 1,
+ };
+
+ enum class InvMemoryLayout : u32 {
+ BlockLinear = 0,
+ Linear = 1,
+ };
+
struct Cull {
enum class FrontFace : u32 {
ClockWise = 0x0900,
@@ -432,7 +442,12 @@ public:
u32 width;
u32 height;
Tegra::RenderTargetFormat format;
- u32 block_dimensions;
+ union {
+ BitField<0, 3, u32> block_width;
+ BitField<4, 3, u32> block_height;
+ BitField<8, 3, u32> block_depth;
+ BitField<12, 1, InvMemoryLayout> type;
+ } memory_layout;
u32 array_mode;
u32 layer_stride;
u32 base_layer;
@@ -562,7 +577,12 @@ public:
u32 address_high;
u32 address_low;
Tegra::DepthFormat format;
- u32 block_dimensions;
+ union {
+ BitField<0, 4, u32> block_width;
+ BitField<4, 4, u32> block_height;
+ BitField<8, 4, u32> block_depth;
+ BitField<20, 1, InvMemoryLayout> type;
+ } memory_layout;
u32 layer_stride;
GPUVAddr Address() const {
diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp
index aa7481b8c..bf2a21bb6 100644
--- a/src/video_core/engines/maxwell_dma.cpp
+++ b/src/video_core/engines/maxwell_dma.cpp
@@ -68,12 +68,14 @@ void MaxwellDMA::HandleCopy() {
if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
// If the input is tiled and the output is linear, deswizzle the input and copy it over.
- Texture::CopySwizzledData(regs.src_params.size_x, regs.src_params.size_y, 1, 1, src_buffer,
- dst_buffer, true, regs.src_params.BlockHeight());
+ Texture::CopySwizzledData(regs.src_params.size_x, regs.src_params.size_y,
+ regs.src_params.size_z, 1, 1, src_buffer, dst_buffer, true,
+ regs.src_params.BlockHeight(), regs.src_params.BlockDepth());
} else {
// If the input is linear and the output is tiled, swizzle the input and copy it over.
- Texture::CopySwizzledData(regs.dst_params.size_x, regs.dst_params.size_y, 1, 1, dst_buffer,
- src_buffer, false, regs.dst_params.BlockHeight());
+ Texture::CopySwizzledData(regs.dst_params.size_x, regs.dst_params.size_y,
+ regs.dst_params.size_z, 1, 1, dst_buffer, src_buffer, false,
+ regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
}
}
diff --git a/src/video_core/engines/maxwell_dma.h b/src/video_core/engines/maxwell_dma.h
index 311ccb616..df19e02e2 100644
--- a/src/video_core/engines/maxwell_dma.h
+++ b/src/video_core/engines/maxwell_dma.h
@@ -43,6 +43,10 @@ public:
u32 BlockHeight() const {
return 1 << block_height;
}
+
+ u32 BlockDepth() const {
+ return 1 << block_depth;
+ }
};
static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 550ab1148..f356f9a03 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -214,6 +214,18 @@ enum class IMinMaxExchange : u64 {
XHi = 3,
};
+enum class VmadType : u64 {
+ Size16_Low = 0,
+ Size16_High = 1,
+ Size32 = 2,
+ Invalid = 3,
+};
+
+enum class VmadShr : u64 {
+ Shr7 = 1,
+ Shr15 = 2,
+};
+
enum class XmadMode : u64 {
None = 0,
CLo = 1,
@@ -255,7 +267,7 @@ enum class ControlCode : u64 {
GTU = 12,
NEU = 13,
GEU = 14,
- //
+ T = 15,
OFF = 16,
LO = 17,
SFF = 18,
@@ -452,6 +464,7 @@ union Instruction {
BitField<48, 16, u64> opcode;
union {
+ BitField<20, 16, u64> imm20_16;
BitField<20, 19, u64> imm20_19;
BitField<20, 32, s64> imm20_32;
BitField<45, 1, u64> negate_b;
@@ -493,6 +506,10 @@ union Instruction {
}
} lop3;
+ u16 GetImm20_16() const {
+ return static_cast<u16>(imm20_16);
+ }
+
u32 GetImm20_19() const {
u32 imm{static_cast<u32>(imm20_19)};
imm <<= 12;
@@ -1017,6 +1034,23 @@ union Instruction {
} isberd;
union {
+ BitField<48, 1, u64> signed_a;
+ BitField<38, 1, u64> is_byte_chunk_a;
+ BitField<36, 2, VmadType> type_a;
+ BitField<36, 2, u64> byte_height_a;
+
+ BitField<49, 1, u64> signed_b;
+ BitField<50, 1, u64> use_register_b;
+ BitField<30, 1, u64> is_byte_chunk_b;
+ BitField<28, 2, VmadType> type_b;
+ BitField<28, 2, u64> byte_height_b;
+
+ BitField<51, 2, VmadShr> shr;
+ BitField<55, 1, u64> saturate; // Saturates the result (a * b + c)
+ BitField<47, 1, u64> cc;
+ } vmad;
+
+ union {
BitField<20, 16, u64> imm20_16;
BitField<36, 1, u64> product_shift_left;
BitField<37, 1, u64> merge_37;
@@ -1083,6 +1117,7 @@ public:
IPA,
OUT_R, // Emit vertex/primitive
ISBERD,
+ VMAD,
FFMA_IMM, // Fused Multiply and Add
FFMA_CR,
FFMA_RC,
@@ -1320,6 +1355,7 @@ private:
INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
+ INST("01011111--------", Id::VMAD, Type::Trivial, "VMAD"),
INST("0011001-1-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index 84582c777..8d5f277e2 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -286,7 +286,8 @@ void RasterizerOpenGL::SetupShaders(GLenum primitive_mode) {
&ubo, sizeof(ubo), static_cast<std::size_t>(uniform_buffer_alignment));
// Bind the buffer
- glBindBufferRange(GL_UNIFORM_BUFFER, stage, buffer_cache.GetHandle(), offset, sizeof(ubo));
+ glBindBufferRange(GL_UNIFORM_BUFFER, static_cast<GLuint>(stage), buffer_cache.GetHandle(),
+ offset, static_cast<GLsizeiptr>(sizeof(ubo)));
Shader shader{shader_cache.GetStageProgram(program)};
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 56ff83eff..801d45144 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -45,7 +45,9 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
SurfaceParams params{};
params.addr = TryGetCpuAddr(config.tic.Address());
params.is_tiled = config.tic.IsTiled();
+ params.block_width = params.is_tiled ? config.tic.BlockWidth() : 0,
params.block_height = params.is_tiled ? config.tic.BlockHeight() : 0,
+ params.block_depth = params.is_tiled ? config.tic.BlockDepth() : 0,
params.pixel_format =
PixelFormatFromTextureFormat(config.tic.format, config.tic.r_type.Value());
params.component_type = ComponentTypeFromTexture(config.tic.r_type.Value());
@@ -97,8 +99,11 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
const auto& config{Core::System::GetInstance().GPU().Maxwell3D().regs.rt[index]};
SurfaceParams params{};
params.addr = TryGetCpuAddr(config.Address());
- params.is_tiled = true;
- params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
+ params.is_tiled =
+ config.memory_layout.type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
+ params.block_width = 1 << config.memory_layout.block_width;
+ params.block_height = 1 << config.memory_layout.block_height;
+ params.block_depth = 1 << config.memory_layout.block_depth;
params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
params.component_type = ComponentTypeFromRenderTarget(config.format);
params.type = GetFormatType(params.pixel_format);
@@ -120,13 +125,16 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
return params;
}
-/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
- Tegra::GPUVAddr zeta_address,
- Tegra::DepthFormat format) {
+/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(
+ u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
+ u32 block_width, u32 block_height, u32 block_depth,
+ Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type) {
SurfaceParams params{};
params.addr = TryGetCpuAddr(zeta_address);
- params.is_tiled = true;
- params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
+ params.is_tiled = type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
+ params.block_width = 1 << std::min(block_width, 5U);
+ params.block_height = 1 << std::min(block_height, 5U);
+ params.block_depth = 1 << std::min(block_depth, 5U);
params.pixel_format = PixelFormatFromDepthFormat(format);
params.component_type = ComponentTypeFromDepthFormat(format);
params.type = GetFormatType(params.pixel_format);
@@ -148,7 +156,9 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
SurfaceParams params{};
params.addr = TryGetCpuAddr(config.Address());
params.is_tiled = !config.linear;
- params.block_height = params.is_tiled ? config.BlockHeight() : 0,
+ params.block_width = params.is_tiled ? std::min(config.BlockWidth(), 32U) : 0,
+ params.block_height = params.is_tiled ? std::min(config.BlockHeight(), 32U) : 0,
+ params.block_depth = params.is_tiled ? std::min(config.BlockDepth(), 32U) : 0,
params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
params.component_type = ComponentTypeFromRenderTarget(config.format);
params.type = GetFormatType(params.pixel_format);
@@ -221,6 +231,8 @@ static constexpr std::array<FormatTuple, SurfaceParams::MaxPixelFormat> tex_form
{GL_RG32UI, GL_RG_INTEGER, GL_UNSIGNED_INT, ComponentType::UInt, false}, // RG32UI
{GL_R32UI, GL_RED_INTEGER, GL_UNSIGNED_INT, ComponentType::UInt, false}, // R32UI
{GL_RGBA8, GL_RGBA, GL_UNSIGNED_BYTE, ComponentType::UNorm, false}, // ASTC_2D_8X8
+ {GL_RGBA8, GL_RGBA, GL_UNSIGNED_BYTE, ComponentType::UNorm, false}, // ASTC_2D_8X5
+ {GL_RGBA8, GL_RGBA, GL_UNSIGNED_BYTE, ComponentType::UNorm, false}, // ASTC_2D_5X4
// Depth formats
{GL_DEPTH_COMPONENT32F, GL_DEPTH_COMPONENT, GL_FLOAT, ComponentType::Float, false}, // Z32F
@@ -267,7 +279,9 @@ static const FormatTuple& GetFormatTuple(PixelFormat pixel_format, ComponentType
static bool IsPixelFormatASTC(PixelFormat format) {
switch (format) {
case PixelFormat::ASTC_2D_4X4:
+ case PixelFormat::ASTC_2D_5X4:
case PixelFormat::ASTC_2D_8X8:
+ case PixelFormat::ASTC_2D_8X5:
return true;
default:
return false;
@@ -278,8 +292,12 @@ static std::pair<u32, u32> GetASTCBlockSize(PixelFormat format) {
switch (format) {
case PixelFormat::ASTC_2D_4X4:
return {4, 4};
+ case PixelFormat::ASTC_2D_5X4:
+ return {5, 4};
case PixelFormat::ASTC_2D_8X8:
return {8, 8};
+ case PixelFormat::ASTC_2D_8X5:
+ return {8, 5};
default:
LOG_CRITICAL(HW_GPU, "Unhandled format: {}", static_cast<u32>(format));
UNREACHABLE();
@@ -313,8 +331,8 @@ static bool IsFormatBCn(PixelFormat format) {
}
template <bool morton_to_gl, PixelFormat format>
-void MortonCopy(u32 stride, u32 block_height, u32 height, u8* gl_buffer, std::size_t gl_buffer_size,
- VAddr addr) {
+void MortonCopy(u32 stride, u32 block_height, u32 height, u32 block_depth, u32 depth, u8* gl_buffer,
+ std::size_t gl_buffer_size, VAddr addr) {
constexpr u32 bytes_per_pixel = SurfaceParams::GetFormatBpp(format) / CHAR_BIT;
constexpr u32 gl_bytes_per_pixel = CachedSurface::GetGLBytesPerPixel(format);
@@ -323,7 +341,7 @@ void MortonCopy(u32 stride, u32 block_height, u32 height, u8* gl_buffer, std::si
// pixel values.
const u32 tile_size{IsFormatBCn(format) ? 4U : 1U};
const std::vector<u8> data = Tegra::Texture::UnswizzleTexture(
- addr, tile_size, bytes_per_pixel, stride, height, block_height);
+ addr, tile_size, bytes_per_pixel, stride, height, depth, block_height, block_depth);
const std::size_t size_to_copy{std::min(gl_buffer_size, data.size())};
memcpy(gl_buffer, data.data(), size_to_copy);
} else {
@@ -335,7 +353,7 @@ void MortonCopy(u32 stride, u32 block_height, u32 height, u8* gl_buffer, std::si
}
}
-static constexpr std::array<void (*)(u32, u32, u32, u8*, std::size_t, VAddr),
+static constexpr std::array<void (*)(u32, u32, u32, u32, u32, u8*, std::size_t, VAddr),
SurfaceParams::MaxPixelFormat>
morton_to_gl_fns = {
// clang-format off
@@ -385,6 +403,8 @@ static constexpr std::array<void (*)(u32, u32, u32, u8*, std::size_t, VAddr),
MortonCopy<true, PixelFormat::RG32UI>,
MortonCopy<true, PixelFormat::R32UI>,
MortonCopy<true, PixelFormat::ASTC_2D_8X8>,
+ MortonCopy<true, PixelFormat::ASTC_2D_8X5>,
+ MortonCopy<true, PixelFormat::ASTC_2D_5X4>,
MortonCopy<true, PixelFormat::Z32F>,
MortonCopy<true, PixelFormat::Z16>,
MortonCopy<true, PixelFormat::Z24S8>,
@@ -393,7 +413,7 @@ static constexpr std::array<void (*)(u32, u32, u32, u8*, std::size_t, VAddr),
// clang-format on
};
-static constexpr std::array<void (*)(u32, u32, u32, u8*, std::size_t, VAddr),
+static constexpr std::array<void (*)(u32, u32, u32, u32, u32, u8*, std::size_t, VAddr),
SurfaceParams::MaxPixelFormat>
gl_to_morton_fns = {
// clang-format off
@@ -445,6 +465,8 @@ static constexpr std::array<void (*)(u32, u32, u32, u8*, std::size_t, VAddr),
MortonCopy<false, PixelFormat::RG32UI>,
MortonCopy<false, PixelFormat::R32UI>,
nullptr,
+ nullptr,
+ nullptr,
MortonCopy<false, PixelFormat::Z32F>,
MortonCopy<false, PixelFormat::Z16>,
MortonCopy<false, PixelFormat::Z24S8>,
@@ -780,7 +802,9 @@ static void ConvertFormatAsNeeded_LoadGLBuffer(std::vector<u8>& data, PixelForma
u32 width, u32 height) {
switch (pixel_format) {
case PixelFormat::ASTC_2D_4X4:
- case PixelFormat::ASTC_2D_8X8: {
+ case PixelFormat::ASTC_2D_8X8:
+ case PixelFormat::ASTC_2D_8X5:
+ case PixelFormat::ASTC_2D_5X4: {
// Convert ASTC pixel formats to RGBA8, as most desktop GPUs do not support ASTC.
u32 block_width{};
u32 block_height{};
@@ -817,31 +841,23 @@ void CachedSurface::LoadGLBuffer() {
if (params.is_tiled) {
gl_buffer.resize(total_size);
+ u32 depth = params.depth;
+ u32 block_depth = params.block_depth;
- // TODO(bunnei): This only unswizzles and copies a 2D texture - we do not yet know how to do
- // this for 3D textures, etc.
- switch (params.target) {
- case SurfaceParams::SurfaceTarget::Texture2D:
- // Pass impl. to the fallback code below
- break;
- case SurfaceParams::SurfaceTarget::Texture2DArray:
- case SurfaceParams::SurfaceTarget::TextureCubemap:
- for (std::size_t index = 0; index < params.depth; ++index) {
- const std::size_t offset{index * copy_size};
- morton_to_gl_fns[static_cast<std::size_t>(params.pixel_format)](
- params.width, params.block_height, params.height, gl_buffer.data() + offset,
- copy_size, params.addr + offset);
- }
- break;
- default:
- LOG_CRITICAL(HW_GPU, "Unimplemented tiled load for target={}",
- static_cast<u32>(params.target));
- UNREACHABLE();
+ ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture type {}",
+ params.block_width, static_cast<u32>(params.target));
+
+ if (params.target == SurfaceParams::SurfaceTarget::Texture2D) {
+ // TODO(Blinkhawk): Eliminate this condition once all texture types are implemented.
+ depth = 1U;
+ block_depth = 1U;
}
+ const std::size_t size = copy_size * depth;
+
morton_to_gl_fns[static_cast<std::size_t>(params.pixel_format)](
- params.width, params.block_height, params.height, gl_buffer.data(), copy_size,
- params.addr);
+ params.width, params.block_height, params.height, block_depth, depth, gl_buffer.data(),
+ size, params.addr);
} else {
const u8* const texture_src_data_end{texture_src_data + total_size};
gl_buffer.assign(texture_src_data, texture_src_data_end);
@@ -989,7 +1005,9 @@ Surface RasterizerCacheOpenGL::GetDepthBufferSurface(bool preserve_contents) {
}
SurfaceParams depth_params{SurfaceParams::CreateForDepthBuffer(
- regs.zeta_width, regs.zeta_height, regs.zeta.Address(), regs.zeta.format)};
+ regs.zeta_width, regs.zeta_height, regs.zeta.Address(), regs.zeta.format,
+ regs.zeta.memory_layout.block_width, regs.zeta.memory_layout.block_height,
+ regs.zeta.memory_layout.block_depth, regs.zeta.memory_layout.type)};
return GetSurface(depth_params, preserve_contents);
}
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.h b/src/video_core/renderer_opengl/gl_rasterizer_cache.h
index 0b4940b3c..0b8ae3eb4 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.h
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.h
@@ -74,19 +74,21 @@ struct SurfaceParams {
RG32UI = 43,
R32UI = 44,
ASTC_2D_8X8 = 45,
+ ASTC_2D_8X5 = 46,
+ ASTC_2D_5X4 = 47,
MaxColorFormat,
// Depth formats
- Z32F = 46,
- Z16 = 47,
+ Z32F = 48,
+ Z16 = 49,
MaxDepthFormat,
// DepthStencil formats
- Z24S8 = 48,
- S8Z24 = 49,
- Z32FS8 = 50,
+ Z24S8 = 50,
+ S8Z24 = 51,
+ Z32FS8 = 52,
MaxDepthStencilFormat,
@@ -220,6 +222,8 @@ struct SurfaceParams {
1, // RG32UI
1, // R32UI
4, // ASTC_2D_8X8
+ 4, // ASTC_2D_8X5
+ 4, // ASTC_2D_5X4
1, // Z32F
1, // Z16
1, // Z24S8
@@ -282,6 +286,8 @@ struct SurfaceParams {
64, // RG32UI
32, // R32UI
16, // ASTC_2D_8X8
+ 32, // ASTC_2D_8X5
+ 32, // ASTC_2D_5X4
32, // Z32F
16, // Z16
32, // Z24S8
@@ -553,8 +559,12 @@ struct SurfaceParams {
return PixelFormat::BC6H_SF16;
case Tegra::Texture::TextureFormat::ASTC_2D_4X4:
return PixelFormat::ASTC_2D_4X4;
+ case Tegra::Texture::TextureFormat::ASTC_2D_5X4:
+ return PixelFormat::ASTC_2D_5X4;
case Tegra::Texture::TextureFormat::ASTC_2D_8X8:
return PixelFormat::ASTC_2D_8X8;
+ case Tegra::Texture::TextureFormat::ASTC_2D_8X5:
+ return PixelFormat::ASTC_2D_8X5;
case Tegra::Texture::TextureFormat::R16_G16:
switch (component_type) {
case Tegra::Texture::ComponentType::FLOAT:
@@ -716,9 +726,10 @@ struct SurfaceParams {
static SurfaceParams CreateForFramebuffer(std::size_t index);
/// Creates SurfaceParams for a depth buffer configuration
- static SurfaceParams CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
- Tegra::GPUVAddr zeta_address,
- Tegra::DepthFormat format);
+ static SurfaceParams CreateForDepthBuffer(
+ u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
+ u32 block_width, u32 block_height, u32 block_depth,
+ Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type);
/// Creates SurfaceParams for a Fermi2D surface copy
static SurfaceParams CreateForFermiCopySurface(
@@ -733,7 +744,9 @@ struct SurfaceParams {
VAddr addr;
bool is_tiled;
+ u32 block_width;
u32 block_height;
+ u32 block_depth;
PixelFormat pixel_format;
ComponentType component_type;
SurfaceType type;
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index c82a0dcfa..ca063d90d 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -1436,7 +1436,6 @@ private:
break;
}
-
case OpCode::Type::Shift: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true);
std::string op_b;
@@ -1478,7 +1477,6 @@ private:
}
break;
}
-
case OpCode::Type::ArithmeticIntegerImmediate: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
std::string op_b = std::to_string(instr.alu.imm20_32.Value());
@@ -2626,14 +2624,14 @@ private:
const std::string pred =
GetPredicateCondition(instr.csetp.pred39, instr.csetp.neg_pred39 != 0);
const std::string combiner = GetPredicateCombiner(instr.csetp.op);
- const std::string controlCode = regs.GetControlCode(instr.csetp.cc);
+ const std::string control_code = regs.GetControlCode(instr.csetp.cc);
if (instr.csetp.pred3 != static_cast<u64>(Pred::UnusedIndex)) {
SetPredicate(instr.csetp.pred3,
- '(' + controlCode + ") " + combiner + " (" + pred + ')');
+ '(' + control_code + ") " + combiner + " (" + pred + ')');
}
if (instr.csetp.pred0 != static_cast<u64>(Pred::UnusedIndex)) {
SetPredicate(instr.csetp.pred0,
- "!(" + controlCode + ") " + combiner + " (" + pred + ')');
+ "!(" + control_code + ") " + combiner + " (" + pred + ')');
}
break;
}
@@ -2953,6 +2951,88 @@ private:
LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed");
break;
}
+ case OpCode::Id::VMAD: {
+ const bool signed_a = instr.vmad.signed_a == 1;
+ const bool signed_b = instr.vmad.signed_b == 1;
+ const bool result_signed = signed_a || signed_b;
+ boost::optional<std::string> forced_result;
+
+ auto Unpack = [&](const std::string& op, bool is_chunk, bool is_signed,
+ Tegra::Shader::VmadType type, u64 byte_height) {
+ const std::string value = [&]() {
+ if (!is_chunk) {
+ const auto offset = static_cast<u32>(byte_height * 8);
+ return "((" + op + " >> " + std::to_string(offset) + ") & 0xff)";
+ }
+ const std::string zero = "0";
+
+ switch (type) {
+ case Tegra::Shader::VmadType::Size16_Low:
+ return '(' + op + " & 0xffff)";
+ case Tegra::Shader::VmadType::Size16_High:
+ return '(' + op + " >> 16)";
+ case Tegra::Shader::VmadType::Size32:
+ // TODO(Rodrigo): From my hardware tests it becomes a bit "mad" when
+ // this type is used (1 * 1 + 0 == 0x5b800000). Until a better
+ // explanation is found: assert.
+ UNREACHABLE_MSG("Unimplemented");
+ return zero;
+ case Tegra::Shader::VmadType::Invalid:
+ // Note(Rodrigo): This flag is invalid according to nvdisasm. From my
+ // testing (even though it's invalid) this makes the whole instruction
+ // assign zero to target register.
+ forced_result = boost::make_optional(zero);
+ return zero;
+ default:
+ UNREACHABLE();
+ return zero;
+ }
+ }();
+
+ if (is_signed) {
+ return "int(" + value + ')';
+ }
+ return value;
+ };
+
+ const std::string op_a = Unpack(regs.GetRegisterAsInteger(instr.gpr8, 0, false),
+ instr.vmad.is_byte_chunk_a != 0, signed_a,
+ instr.vmad.type_a, instr.vmad.byte_height_a);
+
+ std::string op_b;
+ if (instr.vmad.use_register_b) {
+ op_b = Unpack(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
+ instr.vmad.is_byte_chunk_b != 0, signed_b, instr.vmad.type_b,
+ instr.vmad.byte_height_b);
+ } else {
+ op_b = '(' +
+ std::to_string(signed_b ? static_cast<s16>(instr.alu.GetImm20_16())
+ : instr.alu.GetImm20_16()) +
+ ')';
+ }
+
+ const std::string op_c = regs.GetRegisterAsInteger(instr.gpr39, 0, result_signed);
+
+ std::string result;
+ if (forced_result) {
+ result = *forced_result;
+ } else {
+ result = '(' + op_a + " * " + op_b + " + " + op_c + ')';
+
+ switch (instr.vmad.shr) {
+ case Tegra::Shader::VmadShr::Shr7:
+ result = '(' + result + " >> 7)";
+ break;
+ case Tegra::Shader::VmadShr::Shr15:
+ result = '(' + result + " >> 15)";
+ break;
+ }
+ }
+ regs.SetRegisterToInteger(instr.gpr0, result_signed, 1, result, 1, 1,
+ instr.vmad.saturate == 1, 0, Register::Size::Word,
+ instr.vmad.cc);
+ break;
+ }
default: {
LOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", opcode->GetName());
UNREACHABLE();
diff --git a/src/video_core/textures/decoders.cpp b/src/video_core/textures/decoders.cpp
index 3d5476e5d..18ab723f7 100644
--- a/src/video_core/textures/decoders.cpp
+++ b/src/video_core/textures/decoders.cpp
@@ -4,6 +4,7 @@
#include <cmath>
#include <cstring>
+#include "common/alignment.h"
#include "common/assert.h"
#include "core/memory.h"
#include "video_core/gpu.h"
@@ -39,72 +40,146 @@ struct alignas(64) SwizzleTable {
constexpr auto legacy_swizzle_table = SwizzleTable<8, 64, 1>();
constexpr auto fast_swizzle_table = SwizzleTable<8, 4, 16>();
-static void LegacySwizzleData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
- u8* swizzled_data, u8* unswizzled_data, bool unswizzle,
- u32 block_height) {
+/**
+ * This function manages ALL the GOBs(Group of Bytes) Inside a single block.
+ * Instead of going gob by gob, we map the coordinates inside a block and manage from
+ * those. Block_Width is assumed to be 1.
+ */
+void PreciseProcessBlock(u8* swizzled_data, u8* unswizzled_data, const bool unswizzle,
+ const u32 x_start, const u32 y_start, const u32 z_start, const u32 x_end,
+ const u32 y_end, const u32 z_end, const u32 tile_offset,
+ const u32 xy_block_size, const u32 layer_z, const u32 stride_x,
+ const u32 bytes_per_pixel, const u32 out_bytes_per_pixel) {
std::array<u8*, 2> data_ptrs;
- const std::size_t stride = width * bytes_per_pixel;
- const std::size_t gobs_in_x = 64;
- const std::size_t gobs_in_y = 8;
- const std::size_t gobs_size = gobs_in_x * gobs_in_y;
- const std::size_t image_width_in_gobs{(stride + gobs_in_x - 1) / gobs_in_x};
- for (std::size_t y = 0; y < height; ++y) {
- const std::size_t gob_y_address =
- (y / (gobs_in_y * block_height)) * gobs_size * block_height * image_width_in_gobs +
- (y % (gobs_in_y * block_height) / gobs_in_y) * gobs_size;
- const auto& table = legacy_swizzle_table[y % gobs_in_y];
- for (std::size_t x = 0; x < width; ++x) {
- const std::size_t gob_address =
- gob_y_address + (x * bytes_per_pixel / gobs_in_x) * gobs_size * block_height;
- const std::size_t x2 = x * bytes_per_pixel;
- const std::size_t swizzle_offset = gob_address + table[x2 % gobs_in_x];
- const std::size_t pixel_index = (x + y * width) * out_bytes_per_pixel;
-
- data_ptrs[unswizzle] = swizzled_data + swizzle_offset;
- data_ptrs[!unswizzle] = unswizzled_data + pixel_index;
-
- std::memcpy(data_ptrs[0], data_ptrs[1], bytes_per_pixel);
+ u32 z_address = tile_offset;
+ const u32 gob_size_x = 64;
+ const u32 gob_size_y = 8;
+ const u32 gob_size_z = 1;
+ const u32 gob_size = gob_size_x * gob_size_y * gob_size_z;
+ for (u32 z = z_start; z < z_end; z++) {
+ u32 y_address = z_address;
+ u32 pixel_base = layer_z * z + y_start * stride_x;
+ for (u32 y = y_start; y < y_end; y++) {
+ const auto& table = legacy_swizzle_table[y % gob_size_y];
+ for (u32 x = x_start; x < x_end; x++) {
+ const u32 swizzle_offset{y_address + table[x * bytes_per_pixel % gob_size_x]};
+ const u32 pixel_index{x * out_bytes_per_pixel + pixel_base};
+ data_ptrs[unswizzle] = swizzled_data + swizzle_offset;
+ data_ptrs[!unswizzle] = unswizzled_data + pixel_index;
+ std::memcpy(data_ptrs[0], data_ptrs[1], bytes_per_pixel);
+ }
+ pixel_base += stride_x;
+ if ((y + 1) % gob_size_y == 0)
+ y_address += gob_size;
}
+ z_address += xy_block_size;
}
}
-static void FastSwizzleData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
- u8* swizzled_data, u8* unswizzled_data, bool unswizzle,
- u32 block_height) {
+/**
+ * This function manages ALL the GOBs(Group of Bytes) Inside a single block.
+ * Instead of going gob by gob, we map the coordinates inside a block and manage from
+ * those. Block_Width is assumed to be 1.
+ */
+void FastProcessBlock(u8* swizzled_data, u8* unswizzled_data, const bool unswizzle,
+ const u32 x_start, const u32 y_start, const u32 z_start, const u32 x_end,
+ const u32 y_end, const u32 z_end, const u32 tile_offset,
+ const u32 xy_block_size, const u32 layer_z, const u32 stride_x,
+ const u32 bytes_per_pixel, const u32 out_bytes_per_pixel) {
std::array<u8*, 2> data_ptrs;
- const std::size_t stride{width * bytes_per_pixel};
- const std::size_t gobs_in_x = 64;
- const std::size_t gobs_in_y = 8;
- const std::size_t gobs_size = gobs_in_x * gobs_in_y;
- const std::size_t image_width_in_gobs{(stride + gobs_in_x - 1) / gobs_in_x};
- const std::size_t copy_size{16};
- for (std::size_t y = 0; y < height; ++y) {
- const std::size_t initial_gob =
- (y / (gobs_in_y * block_height)) * gobs_size * block_height * image_width_in_gobs +
- (y % (gobs_in_y * block_height) / gobs_in_y) * gobs_size;
- const std::size_t pixel_base{y * width * out_bytes_per_pixel};
- const auto& table = fast_swizzle_table[y % gobs_in_y];
- for (std::size_t xb = 0; xb < stride; xb += copy_size) {
- const std::size_t gob_address{initial_gob +
- (xb / gobs_in_x) * gobs_size * block_height};
- const std::size_t swizzle_offset{gob_address + table[(xb / 16) % 4]};
- const std::size_t out_x = xb * out_bytes_per_pixel / bytes_per_pixel;
- const std::size_t pixel_index{out_x + pixel_base};
- data_ptrs[unswizzle] = swizzled_data + swizzle_offset;
- data_ptrs[!unswizzle] = unswizzled_data + pixel_index;
- std::memcpy(data_ptrs[0], data_ptrs[1], copy_size);
+ u32 z_address = tile_offset;
+ const u32 x_startb = x_start * bytes_per_pixel;
+ const u32 x_endb = x_end * bytes_per_pixel;
+ const u32 copy_size = 16;
+ const u32 gob_size_x = 64;
+ const u32 gob_size_y = 8;
+ const u32 gob_size_z = 1;
+ const u32 gob_size = gob_size_x * gob_size_y * gob_size_z;
+ for (u32 z = z_start; z < z_end; z++) {
+ u32 y_address = z_address;
+ u32 pixel_base = layer_z * z + y_start * stride_x;
+ for (u32 y = y_start; y < y_end; y++) {
+ const auto& table = fast_swizzle_table[y % gob_size_y];
+ for (u32 xb = x_startb; xb < x_endb; xb += copy_size) {
+ const u32 swizzle_offset{y_address + table[(xb / copy_size) % 4]};
+ const u32 out_x = xb * out_bytes_per_pixel / bytes_per_pixel;
+ const u32 pixel_index{out_x + pixel_base};
+ data_ptrs[unswizzle] = swizzled_data + swizzle_offset;
+ data_ptrs[!unswizzle] = unswizzled_data + pixel_index;
+ std::memcpy(data_ptrs[0], data_ptrs[1], copy_size);
+ }
+ pixel_base += stride_x;
+ if ((y + 1) % gob_size_y == 0)
+ y_address += gob_size;
}
+ z_address += xy_block_size;
}
}
-void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
- u8* swizzled_data, u8* unswizzled_data, bool unswizzle, u32 block_height) {
+/**
+ * This function unswizzles or swizzles a texture by mapping Linear to BlockLinear Textue.
+ * The body of this function takes care of splitting the swizzled texture into blocks,
+ * and managing the extents of it. Once all the parameters of a single block are obtained,
+ * the function calls 'ProcessBlock' to process that particular Block.
+ *
+ * Documentation for the memory layout and decoding can be found at:
+ * https://envytools.readthedocs.io/en/latest/hw/memory/g80-surface.html#blocklinear-surfaces
+ */
+template <bool fast>
+void SwizzledData(u8* swizzled_data, u8* unswizzled_data, const bool unswizzle, const u32 width,
+ const u32 height, const u32 depth, const u32 bytes_per_pixel,
+ const u32 out_bytes_per_pixel, const u32 block_height, const u32 block_depth) {
+ auto div_ceil = [](const u32 x, const u32 y) { return ((x + y - 1) / y); };
+ const u32 stride_x = width * out_bytes_per_pixel;
+ const u32 layer_z = height * stride_x;
+ const u32 gob_x_bytes = 64;
+ const u32 gob_elements_x = gob_x_bytes / bytes_per_pixel;
+ const u32 gob_elements_y = 8;
+ const u32 gob_elements_z = 1;
+ const u32 block_x_elements = gob_elements_x;
+ const u32 block_y_elements = gob_elements_y * block_height;
+ const u32 block_z_elements = gob_elements_z * block_depth;
+ const u32 blocks_on_x = div_ceil(width, block_x_elements);
+ const u32 blocks_on_y = div_ceil(height, block_y_elements);
+ const u32 blocks_on_z = div_ceil(depth, block_z_elements);
+ const u32 blocks = blocks_on_x * blocks_on_y * blocks_on_z;
+ const u32 gob_size = gob_x_bytes * gob_elements_y * gob_elements_z;
+ const u32 xy_block_size = gob_size * block_height;
+ const u32 block_size = xy_block_size * block_depth;
+ u32 tile_offset = 0;
+ for (u32 zb = 0; zb < blocks_on_z; zb++) {
+ const u32 z_start = zb * block_z_elements;
+ const u32 z_end = std::min(depth, z_start + block_z_elements);
+ for (u32 yb = 0; yb < blocks_on_y; yb++) {
+ const u32 y_start = yb * block_y_elements;
+ const u32 y_end = std::min(height, y_start + block_y_elements);
+ for (u32 xb = 0; xb < blocks_on_x; xb++) {
+ const u32 x_start = xb * block_x_elements;
+ const u32 x_end = std::min(width, x_start + block_x_elements);
+ if (fast) {
+ FastProcessBlock(swizzled_data, unswizzled_data, unswizzle, x_start, y_start,
+ z_start, x_end, y_end, z_end, tile_offset, xy_block_size,
+ layer_z, stride_x, bytes_per_pixel, out_bytes_per_pixel);
+ } else {
+ PreciseProcessBlock(swizzled_data, unswizzled_data, unswizzle, x_start, y_start,
+ z_start, x_end, y_end, z_end, tile_offset, xy_block_size,
+ layer_z, stride_x, bytes_per_pixel, out_bytes_per_pixel);
+ }
+ tile_offset += block_size;
+ }
+ }
+ }
+}
+
+void CopySwizzledData(u32 width, u32 height, u32 depth, u32 bytes_per_pixel,
+ u32 out_bytes_per_pixel, u8* swizzled_data, u8* unswizzled_data,
+ bool unswizzle, u32 block_height, u32 block_depth) {
if (bytes_per_pixel % 3 != 0 && (width * bytes_per_pixel) % 16 == 0) {
- FastSwizzleData(width, height, bytes_per_pixel, out_bytes_per_pixel, swizzled_data,
- unswizzled_data, unswizzle, block_height);
+ SwizzledData<true>(swizzled_data, unswizzled_data, unswizzle, width, height, depth,
+ bytes_per_pixel, out_bytes_per_pixel, block_height, block_depth);
} else {
- LegacySwizzleData(width, height, bytes_per_pixel, out_bytes_per_pixel, swizzled_data,
- unswizzled_data, unswizzle, block_height);
+ SwizzledData<false>(swizzled_data, unswizzled_data, unswizzle, width, height, depth,
+ bytes_per_pixel, out_bytes_per_pixel, block_height, block_depth);
}
}
@@ -125,7 +200,9 @@ u32 BytesPerPixel(TextureFormat format) {
case TextureFormat::R32_G32_B32:
return 12;
case TextureFormat::ASTC_2D_4X4:
+ case TextureFormat::ASTC_2D_5X4:
case TextureFormat::ASTC_2D_8X8:
+ case TextureFormat::ASTC_2D_8X5:
case TextureFormat::A8R8G8B8:
case TextureFormat::A2B10G10R10:
case TextureFormat::BF10GF11RF11:
@@ -152,10 +229,11 @@ u32 BytesPerPixel(TextureFormat format) {
}
std::vector<u8> UnswizzleTexture(VAddr address, u32 tile_size, u32 bytes_per_pixel, u32 width,
- u32 height, u32 block_height) {
- std::vector<u8> unswizzled_data(width * height * bytes_per_pixel);
- CopySwizzledData(width / tile_size, height / tile_size, bytes_per_pixel, bytes_per_pixel,
- Memory::GetPointer(address), unswizzled_data.data(), true, block_height);
+ u32 height, u32 depth, u32 block_height, u32 block_depth) {
+ std::vector<u8> unswizzled_data(width * height * depth * bytes_per_pixel);
+ CopySwizzledData(width / tile_size, height / tile_size, depth, bytes_per_pixel, bytes_per_pixel,
+ Memory::GetPointer(address), unswizzled_data.data(), true, block_height,
+ block_depth);
return unswizzled_data;
}
@@ -199,4 +277,19 @@ std::vector<u8> DecodeTexture(const std::vector<u8>& texture_data, TextureFormat
return rgba_data;
}
+std::size_t CalculateSize(bool tiled, u32 bytes_per_pixel, u32 width, u32 height, u32 depth,
+ u32 block_height, u32 block_depth) {
+ if (tiled) {
+ const u32 gobs_in_x = 64 / bytes_per_pixel;
+ const u32 gobs_in_y = 8;
+ const u32 gobs_in_z = 1;
+ const u32 aligned_width = Common::AlignUp(width, gobs_in_x);
+ const u32 aligned_height = Common::AlignUp(height, gobs_in_y * block_height);
+ const u32 aligned_depth = Common::AlignUp(depth, gobs_in_z * block_depth);
+ return aligned_width * aligned_height * aligned_depth * bytes_per_pixel;
+ } else {
+ return width * height * depth * bytes_per_pixel;
+ }
+}
+
} // namespace Tegra::Texture
diff --git a/src/video_core/textures/decoders.h b/src/video_core/textures/decoders.h
index 1f7b731be..aaf316947 100644
--- a/src/video_core/textures/decoders.h
+++ b/src/video_core/textures/decoders.h
@@ -14,17 +14,14 @@ namespace Tegra::Texture {
* Unswizzles a swizzled texture without changing its format.
*/
std::vector<u8> UnswizzleTexture(VAddr address, u32 tile_size, u32 bytes_per_pixel, u32 width,
- u32 height, u32 block_height = TICEntry::DefaultBlockHeight);
-
-/**
- * Unswizzles a swizzled depth texture without changing its format.
- */
-std::vector<u8> UnswizzleDepthTexture(VAddr address, DepthFormat format, u32 width, u32 height,
- u32 block_height = TICEntry::DefaultBlockHeight);
+ u32 height, u32 depth,
+ u32 block_height = TICEntry::DefaultBlockHeight,
+ u32 block_depth = TICEntry::DefaultBlockHeight);
/// Copies texture data from a buffer and performs swizzling/unswizzling as necessary.
-void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
- u8* swizzled_data, u8* unswizzled_data, bool unswizzle, u32 block_height);
+void CopySwizzledData(u32 width, u32 height, u32 depth, u32 bytes_per_pixel,
+ u32 out_bytes_per_pixel, u8* swizzled_data, u8* unswizzled_data,
+ bool unswizzle, u32 block_height, u32 block_depth);
/**
* Decodes an unswizzled texture into a A8R8G8B8 texture.
@@ -32,4 +29,10 @@ void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_
std::vector<u8> DecodeTexture(const std::vector<u8>& texture_data, TextureFormat format, u32 width,
u32 height);
+/**
+ * This function calculates the correct size of a texture depending if it's tiled or not.
+ */
+std::size_t CalculateSize(bool tiled, u32 bytes_per_pixel, u32 width, u32 height, u32 depth,
+ u32 block_height, u32 block_depth);
+
} // namespace Tegra::Texture
diff --git a/src/video_core/textures/texture.h b/src/video_core/textures/texture.h
index 8f31d825a..5947bd2b9 100644
--- a/src/video_core/textures/texture.h
+++ b/src/video_core/textures/texture.h
@@ -141,6 +141,7 @@ static_assert(sizeof(TextureHandle) == 4, "TextureHandle has wrong size");
struct TICEntry {
static constexpr u32 DefaultBlockHeight = 16;
+ static constexpr u32 DefaultBlockDepth = 1;
union {
u32 raw;
@@ -161,7 +162,9 @@ struct TICEntry {
BitField<21, 3, TICHeaderVersion> header_version;
};
union {
+ BitField<0, 3, u32> block_width;
BitField<3, 3, u32> block_height;
+ BitField<6, 3, u32> block_depth;
// High 16 bits of the pitch value
BitField<0, 16, u32> pitch_high;
@@ -202,13 +205,24 @@ struct TICEntry {
return depth_minus_1 + 1;
}
+ u32 BlockWidth() const {
+ ASSERT(IsTiled());
+ // The block height is stored in log2 format.
+ return 1 << block_width;
+ }
+
u32 BlockHeight() const {
- ASSERT(header_version == TICHeaderVersion::BlockLinear ||
- header_version == TICHeaderVersion::BlockLinearColorKey);
+ ASSERT(IsTiled());
// The block height is stored in log2 format.
return 1 << block_height;
}
+ u32 BlockDepth() const {
+ ASSERT(IsTiled());
+ // The block height is stored in log2 format.
+ return 1 << block_depth;
+ }
+
bool IsTiled() const {
return header_version == TICHeaderVersion::BlockLinear ||
header_version == TICHeaderVersion::BlockLinearColorKey;
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-30 09:59:16 +0000