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-rw-r--r--src/video_core/shader/decode/register_set_predicate.cpp60
-rw-r--r--src/video_core/shader/node.h26
-rw-r--r--src/video_core/shader/shader_ir.cpp6
-rw-r--r--src/video_core/shader/shader_ir.h8
4 files changed, 82 insertions, 18 deletions
diff --git a/src/video_core/shader/decode/register_set_predicate.cpp b/src/video_core/shader/decode/register_set_predicate.cpp
index e6c9d287e..8d54cce34 100644
--- a/src/video_core/shader/decode/register_set_predicate.cpp
+++ b/src/video_core/shader/decode/register_set_predicate.cpp
@@ -13,37 +13,65 @@ namespace VideoCommon::Shader {
using Tegra::Shader::Instruction;
using Tegra::Shader::OpCode;
+namespace {
+constexpr u64 NUM_PROGRAMMABLE_PREDICATES = 7;
+}
+
u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
- UNIMPLEMENTED_IF(instr.r2p.mode != Tegra::Shader::R2pMode::Pr);
+ UNIMPLEMENTED_IF(instr.p2r_r2p.mode != Tegra::Shader::R2pMode::Pr);
- const Node apply_mask = [&]() {
+ const Node apply_mask = [&] {
switch (opcode->get().GetId()) {
case OpCode::Id::R2P_IMM:
- return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
+ case OpCode::Id::P2R_IMM:
+ return Immediate(static_cast<u32>(instr.p2r_r2p.immediate_mask));
default:
UNREACHABLE();
- return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
+ return Immediate(0);
}
}();
- const Node mask = GetRegister(instr.gpr8);
- const auto offset = static_cast<u32>(instr.r2p.byte) * 8;
- constexpr u32 programmable_preds = 7;
- for (u64 pred = 0; pred < programmable_preds; ++pred) {
- const auto shift = static_cast<u32>(pred);
+ const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
+
+ switch (opcode->get().GetId()) {
+ case OpCode::Id::R2P_IMM: {
+ const Node mask = GetRegister(instr.gpr8);
- const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
- const Node condition =
- Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
+ for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
+ const auto shift = static_cast<u32>(pred);
- const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
- const Node value = Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
+ const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
+ const Node condition =
+ Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
- const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
- bb.push_back(Conditional(condition, {code}));
+ const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
+ const Node value =
+ Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
+
+ const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
+ bb.push_back(Conditional(condition, {code}));
+ }
+ break;
+ }
+ case OpCode::Id::P2R_IMM: {
+ Node value = Immediate(0);
+ for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
+ Node bit = Operation(OperationCode::Select, GetPredicate(pred), Immediate(1U << pred),
+ Immediate(0));
+ value = Operation(OperationCode::UBitwiseOr, std::move(value), std::move(bit));
+ }
+ value = Operation(OperationCode::UBitwiseAnd, std::move(value), apply_mask);
+ value = BitfieldInsert(GetRegister(instr.gpr8), std::move(value), offset, 8);
+
+ SetRegister(bb, instr.gpr0, std::move(value));
+ break;
+ }
+ default:
+ UNIMPLEMENTED_MSG("Unhandled P2R/R2R instruction: {}", opcode->get().GetName());
+ break;
}
return pc;
diff --git a/src/video_core/shader/node.h b/src/video_core/shader/node.h
index 4d2f4d6a8..4e155542a 100644
--- a/src/video_core/shader/node.h
+++ b/src/video_core/shader/node.h
@@ -392,8 +392,30 @@ struct MetaImage {
using Meta =
std::variant<MetaArithmetic, MetaTexture, MetaImage, MetaStackClass, Tegra::Shader::HalfType>;
+class AmendNode {
+public:
+ std::optional<std::size_t> GetAmendIndex() const {
+ if (amend_index == amend_null_index) {
+ return std::nullopt;
+ }
+ return {amend_index};
+ }
+
+ void SetAmendIndex(std::size_t index) {
+ amend_index = index;
+ }
+
+ void ClearAmend() {
+ amend_index = amend_null_index;
+ }
+
+private:
+ static constexpr std::size_t amend_null_index = 0xFFFFFFFFFFFFFFFFULL;
+ std::size_t amend_index{amend_null_index};
+};
+
/// Holds any kind of operation that can be done in the IR
-class OperationNode final {
+class OperationNode final : public AmendNode {
public:
explicit OperationNode(OperationCode code) : OperationNode(code, Meta{}) {}
@@ -433,7 +455,7 @@ private:
};
/// Encloses inside any kind of node that returns a boolean conditionally-executed code
-class ConditionalNode final {
+class ConditionalNode final : public AmendNode {
public:
explicit ConditionalNode(Node condition, std::vector<Node>&& code)
: condition{std::move(condition)}, code{std::move(code)} {}
diff --git a/src/video_core/shader/shader_ir.cpp b/src/video_core/shader/shader_ir.cpp
index 1d9825c76..31eecb3f4 100644
--- a/src/video_core/shader/shader_ir.cpp
+++ b/src/video_core/shader/shader_ir.cpp
@@ -446,4 +446,10 @@ Node ShaderIR::BitfieldInsert(Node base, Node insert, u32 offset, u32 bits) {
Immediate(bits));
}
+std::size_t ShaderIR::DeclareAmend(Node new_amend) {
+ const std::size_t id = amend_code.size();
+ amend_code.push_back(new_amend);
+ return id;
+}
+
} // namespace VideoCommon::Shader
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index baed06ccd..aacd0a0da 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -176,6 +176,10 @@ public:
/// Returns a condition code evaluated from internal flags
Node GetConditionCode(Tegra::Shader::ConditionCode cc) const;
+ const Node& GetAmendNode(std::size_t index) const {
+ return amend_code[index];
+ }
+
private:
friend class ASTDecoder;
@@ -392,6 +396,9 @@ private:
Tegra::Shader::Instruction instr,
bool is_write);
+ /// Register new amending code and obtain the reference id.
+ std::size_t DeclareAmend(Node new_amend);
+
const ProgramCode& program_code;
const u32 main_offset;
const CompilerSettings settings;
@@ -406,6 +413,7 @@ private:
std::map<u32, NodeBlock> basic_blocks;
NodeBlock global_code;
ASTManager program_manager{true, true};
+ std::vector<Node> amend_code;
std::set<u32> used_registers;
std::set<Tegra::Shader::Pred> used_predicates;