diff options
Diffstat (limited to 'src/core/hw')
| -rw-r--r-- | src/core/hw/gpu.cpp | 137 | ||||
| -rw-r--r-- | src/core/hw/gpu.h | 18 |
2 files changed, 97 insertions, 58 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index bd7d92cd1..424ce2ca7 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -18,8 +18,9 @@ #include "core/hw/gpu.h" #include "video_core/command_processor.h" +#include "video_core/utils.h" #include "video_core/video_core.h" - +#include <video_core/color.h> namespace GPU { @@ -112,61 +113,109 @@ inline void Write(u32 addr, const T data) { { const auto& config = g_regs.display_transfer_config; if (config.trigger & 1) { - u8* source_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalInputAddress())); - u8* dest_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalOutputAddress())); - - // Cheap emulation of horizontal scaling: Just skip each second pixel of the - // input framebuffer. We keep track of this in the pixel_skip variable. - unsigned pixel_skip = (config.scale_horizontally != 0) ? 2 : 1; - - u32 output_width = config.output_width / pixel_skip; - - for (u32 y = 0; y < config.output_height; ++y) { - // TODO: Why does the register seem to hold twice the framebuffer width? + u8* src_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalInputAddress())); + u8* dst_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalOutputAddress())); + + unsigned horizontal_scale = (config.scale_horizontally != 0) ? 2 : 1; + unsigned vertical_scale = (config.scale_vertically != 0) ? 2 : 1; + + u32 output_width = config.output_width / horizontal_scale; + u32 output_height = config.output_height / vertical_scale; + + if (config.raw_copy) { + // Raw copies do not perform color conversion nor tiled->linear / linear->tiled conversions + // TODO(Subv): Verify if raw copies perform scaling + memcpy(dst_pointer, src_pointer, config.output_width * config.output_height * + GPU::Regs::BytesPerPixel(config.output_format)); + + LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), flags 0x%08X, Raw copy", + config.output_height * output_width * GPU::Regs::BytesPerPixel(config.output_format), + config.GetPhysicalInputAddress(), config.input_width.Value(), config.input_height.Value(), + config.GetPhysicalOutputAddress(), config.output_width.Value(), config.output_height.Value(), + config.output_format.Value(), config.flags); + + GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF); + break; + } + // TODO(Subv): Blend the pixels when horizontal / vertical scaling is enabled, + // right now we're just skipping the extra pixels. + for (u32 y = 0; y < output_height; ++y) { for (u32 x = 0; x < output_width; ++x) { - struct { - int r, g, b, a; - } source_color = { 0, 0, 0, 0 }; + Math::Vec4<u8> src_color = { 0, 0, 0, 0 }; + + u32 scaled_x = x * horizontal_scale; + u32 scaled_y = y * vertical_scale; + + u32 dst_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.output_format); + u32 src_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.input_format); + u32 src_offset; + u32 dst_offset; + + if (config.output_tiled) { + // Interpret the input as linear and the output as tiled + u32 coarse_y = y & ~7; + u32 stride = output_width * dst_bytes_per_pixel; + + src_offset = (scaled_x + scaled_y * config.input_width) * src_bytes_per_pixel; + dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) + coarse_y * stride; + } else { + // Interpret the input as tiled and the output as linear + u32 coarse_y = scaled_y & ~7; + u32 stride = config.input_width * src_bytes_per_pixel; + + src_offset = VideoCore::GetMortonOffset(scaled_x, scaled_y, src_bytes_per_pixel) + coarse_y * stride; + dst_offset = (x + y * output_width) * dst_bytes_per_pixel; + } + const u8* src_pixel = src_pointer + src_offset; switch (config.input_format) { case Regs::PixelFormat::RGBA8: - { - // TODO: Most likely got the component order messed up. - u8* srcptr = source_pointer + (x * pixel_skip + y * config.input_width) * 4; - source_color.r = srcptr[0]; // blue - source_color.g = srcptr[1]; // green - source_color.b = srcptr[2]; // red - source_color.a = srcptr[3]; // alpha + src_color = Color::DecodeRGBA8(src_pixel); + break; + + case Regs::PixelFormat::RGB8: + src_color = Color::DecodeRGB8(src_pixel); + break; + + case Regs::PixelFormat::RGB565: + src_color = Color::DecodeRGB565(src_pixel); + break; + + case Regs::PixelFormat::RGB5A1: + src_color = Color::DecodeRGB5A1(src_pixel); + break; + + case Regs::PixelFormat::RGBA4: + src_color = Color::DecodeRGBA4(src_pixel); break; - } default: LOG_ERROR(HW_GPU, "Unknown source framebuffer format %x", config.input_format.Value()); break; } + u8* dst_pixel = dst_pointer + dst_offset; switch (config.output_format) { - /*case Regs::PixelFormat::RGBA8: - { - // TODO: Untested - u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4); - dstptr[0] = source_color.r; - dstptr[1] = source_color.g; - dstptr[2] = source_color.b; - dstptr[3] = source_color.a; + case Regs::PixelFormat::RGBA8: + Color::EncodeRGBA8(src_color, dst_pixel); break; - }*/ case Regs::PixelFormat::RGB8: - { - // TODO: Most likely got the component order messed up. - u8* dstptr = dest_pointer + (x + y * output_width) * 3; - dstptr[0] = source_color.r; // blue - dstptr[1] = source_color.g; // green - dstptr[2] = source_color.b; // red + Color::EncodeRGB8(src_color, dst_pixel); + break; + + case Regs::PixelFormat::RGB565: + Color::EncodeRGB565(src_color, dst_pixel); + break; + + case Regs::PixelFormat::RGB5A1: + Color::EncodeRGB5A1(src_color, dst_pixel); + break; + + case Regs::PixelFormat::RGBA4: + Color::EncodeRGBA4(src_color, dst_pixel); break; - } default: LOG_ERROR(HW_GPU, "Unknown destination framebuffer format %x", config.output_format.Value()); @@ -175,11 +224,11 @@ inline void Write(u32 addr, const T data) { } } - LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), dst format %x", - config.output_height * output_width * 4, - config.GetPhysicalInputAddress(), (u32)config.input_width, (u32)config.input_height, - config.GetPhysicalOutputAddress(), (u32)output_width, (u32)config.output_height, - config.output_format.Value()); + LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), dst format %x, flags 0x%08X", + config.output_height * output_width * GPU::Regs::BytesPerPixel(config.output_format), + config.GetPhysicalInputAddress(), config.input_width.Value(), config.input_height.Value(), + config.GetPhysicalOutputAddress(), output_width, output_height, + config.output_format.Value(), config.flags); GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF); } diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index df9aa0d71..737b1e968 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -34,13 +34,6 @@ namespace GPU { // MMIO region 0x1EFxxxxx struct Regs { -// helper macro to properly align structure members. -// Calling INSERT_PADDING_WORDS will add a new member variable with a name like "pad121", -// depending on the current source line to make sure variable names are unique. -#define INSERT_PADDING_WORDS_HELPER1(x, y) x ## y -#define INSERT_PADDING_WORDS_HELPER2(x, y) INSERT_PADDING_WORDS_HELPER1(x, y) -#define INSERT_PADDING_WORDS(num_words) u32 INSERT_PADDING_WORDS_HELPER2(pad, __LINE__)[(num_words)] - // helper macro to make sure the defined structures are of the expected size. #if defined(_MSC_VER) // TODO: MSVC does not support using sizeof() on non-static data members even though this @@ -53,7 +46,7 @@ struct Regs { "Structure size and register block length don't match") #endif - // All of those formats are described in reverse byte order, since the 3DS is little-endian. + // Components are laid out in reverse byte order, most significant bits first. enum class PixelFormat : u32 { RGBA8 = 0, RGB8 = 1, @@ -199,12 +192,13 @@ struct Regs { u32 flags; BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true + BitField< 1, 1, u32> output_tiled; // Converts from linear to tiled format + BitField< 3, 1, u32> raw_copy; // Copies the data without performing any processing BitField< 8, 3, PixelFormat> input_format; BitField<12, 3, PixelFormat> output_format; - BitField<16, 1, u32> output_tiled; // stores output in a tiled format - // TODO: Not really sure if this actually scales, or even resizes at all. BitField<24, 1, u32> scale_horizontally; + BitField<25, 1, u32> scale_vertically; }; INSERT_PADDING_WORDS(0x1); @@ -238,10 +232,6 @@ struct Regs { INSERT_PADDING_WORDS(0x9c3); -#undef INSERT_PADDING_WORDS_HELPER1 -#undef INSERT_PADDING_WORDS_HELPER2 -#undef INSERT_PADDING_WORDS - static inline size_t NumIds() { return sizeof(Regs) / sizeof(u32); } |