3 files changed, 73 insertions, 12 deletions

diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 3b7209418..d3bd4a9a3 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -103,6 +103,8 @@ public:
         return num_instructions;
     }
 
+    s64 down_count; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop
+
 protected:
 
     /**
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index a838fd25a..c779e3fd4 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -9,6 +9,8 @@
 #include "core/arm/dyncom/arm_dyncom.h"
 #include "core/arm/dyncom/arm_dyncom_interpreter.h"
 
+#include "core/core_timing.h"
+
 const static cpu_config_t s_arm11_cpu_info = {
     "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
 };
@@ -77,6 +79,9 @@ u64 ARM_DynCom::GetTicks() const {
 
 void ARM_DynCom::AddTicks(u64 ticks) {
     this->ticks += ticks;
+    down_count -= ticks;
+    if (down_count < 0)
+        CoreTiming::Advance();
 }
 
 void ARM_DynCom::ExecuteInstructions(int num_instructions) {
@@ -85,7 +90,8 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
     // Dyncom only breaks on instruction dispatch. This only happens on every instruction when
     // executing one instruction at a time. Otherwise, if a block is being executed, more
     // instructions may actually be executed than specified.
-    ticks += InterpreterMainLoop(state.get());
+    unsigned ticks_executed = InterpreterMainLoop(state.get());
+    AddTicks(ticks_executed);
 }
 
 void ARM_DynCom::SaveContext(ThreadContext& ctx) {
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 9b291862c..7c710ccde 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -947,6 +947,15 @@ typedef struct _smla_inst {
     unsigned int Rn;
 } smla_inst;
 
+typedef struct smlalxy_inst {
+    unsigned int x;
+    unsigned int y;
+    unsigned int RdLo;
+    unsigned int RdHi;
+    unsigned int Rm;
+    unsigned int Rn;
+} smlalxy_inst;
+
 typedef struct ssat_inst {
     unsigned int Rn;
     unsigned int Rd;
@@ -2403,7 +2412,25 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
     return inst_base;
 }
 
-ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); }
+ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index)
+{
+    arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst));
+    smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
+
+    inst_base->cond     = BITS(inst, 28, 31);
+    inst_base->idx      = index;
+    inst_base->br       = NON_BRANCH;
+    inst_base->load_r15 = 0;
+
+    inst_cream->x    = BIT(inst, 5);
+    inst_cream->y    = BIT(inst, 6);
+    inst_cream->RdLo = BITS(inst, 12, 15);
+    inst_cream->RdHi = BITS(inst, 16, 19);
+    inst_cream->Rn   = BITS(inst, 0, 4);
+    inst_cream->Rm   = BITS(inst, 8, 11);
+
+    return inst_base;
+}
 
 ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index)
 {
@@ -5686,6 +5713,34 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
     }
 
     SMLALXY_INST:
+    {
+        if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+            smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
+
+            u64 operand1 = RN;
+            u64 operand2 = RM;
+
+            if (inst_cream->x != 0)
+                operand1 >>= 16;
+            if (inst_cream->y != 0)
+                operand2 >>= 16;
+            operand1 &= 0xFFFF;
+            if (operand1 & 0x8000)
+                operand1 -= 65536;
+            operand2 &= 0xFFFF;
+            if (operand2 & 0x8000)
+                operand2 -= 65536;
+
+            u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2);
+            RDLO = (dest & 0xFFFFFFFF);
+            RDHI = ((dest >> 32) & 0xFFFFFFFF);
+        }
+
+        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        INC_PC(sizeof(smlalxy_inst));
+        FETCH_INST;
+        GOTO_NEXT_INST;
+    }
 
     SMLAW_INST:
     {
@@ -5836,16 +5891,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
 
     SMULW_INST:
     {
-        if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
-            smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
-            int64_t rm = RM;
-            int64_t rn = RN;
-            if (inst_cream->m)
-                rm = BITS(rm, 16, 31);
-            else
-                rm = BITS(rm, 0, 15);
-            int64_t rst = rm * rn;
-            RD = BITS(rst, 16, 47);
+        if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+            smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
+
+            s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF);
+
+            s64 result = (s64)rm * (s64)(s32)RN;
+            RD = BITS(result, 16, 47);
         }
         cpu->Reg[15] += GET_INST_SIZE(cpu);
         INC_PC(sizeof(smlad_inst));
@@ -6267,6 +6319,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
             addr = RN;
             unsigned int value = Memory::Read8(addr);
             Memory::Write8(addr, (RM & 0xFF));
+            RD = value;
         }
         cpu->Reg[15] += GET_INST_SIZE(cpu);
         INC_PC(sizeof(swp_inst));