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-rw-r--r--src/core/arm/arm_interface.h11
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp8
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp587
-rw-r--r--src/core/arm/dyncom/arm_dyncom_run.h4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.h2
-rw-r--r--src/core/arm/skyeye_common/armstate.cpp35
-rw-r--r--src/core/arm/skyeye_common/armstate.h24
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp12
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h2
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp_helper.h32
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp76
11 files changed, 386 insertions, 407 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 5cffe513c..533067d4f 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -14,10 +14,6 @@ namespace Core {
/// Generic ARM11 CPU interface
class ARM_Interface : NonCopyable {
public:
- ARM_Interface() {
- num_instructions = 0;
- }
-
virtual ~ARM_Interface() {
}
@@ -146,11 +142,11 @@ public:
virtual void PrepareReschedule() = 0;
/// Getter for num_instructions
- u64 GetNumInstructions() {
+ u64 GetNumInstructions() const {
return num_instructions;
}
- s64 down_count; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop
+ s64 down_count = 0; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop
protected:
@@ -162,6 +158,5 @@ protected:
private:
- u64 num_instructions; ///< Number of instructions executed
-
+ u64 num_instructions = 0; ///< Number of instructions executed
};
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index ee4288314..8cd6755cb 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -6,10 +6,9 @@
#include "core/arm/skyeye_common/armsupp.h"
const InstructionSetEncodingItem arm_instruction[] = {
- { "vmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }},
- { "vmls", 7, ARMVFP2, { 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0 }},
- { "vnmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0 }},
- { "vnmla", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }},
+ { "vmla", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }},
+ { "vmls", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }},
+ { "vnmla", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }},
{ "vnmls", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }},
{ "vnmul", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }},
{ "vmul", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }},
@@ -211,7 +210,6 @@ const InstructionSetEncodingItem arm_exclusion_code[] = {
{ "vmla", 0, ARMVFP2, { 0 }},
{ "vmls", 0, ARMVFP2, { 0 }},
{ "vnmla", 0, ARMVFP2, { 0 }},
- { "vnmla", 0, ARMVFP2, { 0 }},
{ "vnmls", 0, ARMVFP2, { 0 }},
{ "vnmul", 0, ARMVFP2, { 0 }},
{ "vmul", 0, ARMVFP2, { 0 }},
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index fbd6f94f9..5f8826034 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -23,6 +23,8 @@
#include "core/arm/skyeye_common/armsupp.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
+#include "core/gdbstub/gdbstub.h"
+
Common::Profiling::TimingCategory profile_execute("DynCom::Execute");
Common::Profiling::TimingCategory profile_decode("DynCom::Decode");
@@ -49,7 +51,7 @@ enum {
typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
-static bool CondPassed(ARMul_State* cpu, unsigned int cond) {
+static bool CondPassed(const ARMul_State* cpu, unsigned int cond) {
const bool n_flag = cpu->NFlag != 0;
const bool z_flag = cpu->ZFlag != 0;
const bool c_flag = cpu->CFlag != 0;
@@ -1621,9 +1623,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index)
@@ -1644,9 +1643,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index)
DEBUG_MSG;
}
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index)
@@ -1701,9 +1697,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index)
@@ -1718,9 +1711,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index)
@@ -1735,9 +1725,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
@@ -2595,9 +2582,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index)
@@ -2643,9 +2627,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index)
@@ -2667,9 +2648,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index)
DEBUG_MSG;
}
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){
@@ -2683,9 +2661,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index)
@@ -2727,9 +2702,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index)
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
@@ -2755,9 +2727,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
DEBUG_MSG;
}
- if (BITS(inst, 12, 15) == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index)
@@ -2806,9 +2775,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index)
inst_cream->Rd = BITS(inst, 12, 15);
inst_cream->Rm = BITS(inst, 0, 3);
- if (inst_cream->Rd == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){
@@ -2823,9 +2789,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){
inst_cream->Rd = BITS(inst, 12, 15);
inst_cream->Rm = BITS(inst, 0, 3);
- if (inst_cream->Rd == 15) {
- inst_base->br = INDIRECT_BRANCH;
- }
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){
@@ -2913,9 +2876,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index)
inst_cream->shifter_operand = BITS(inst, 0, 11);
inst_cream->shtop_func = get_shtop(inst);
- if (inst_cream->Rd == 15)
- inst_base->br = INDIRECT_BRANCH;
-
return inst_base;
}
@@ -3242,7 +3202,6 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(vmla),
INTERPRETER_TRANSLATE(vmls),
INTERPRETER_TRANSLATE(vnmla),
- INTERPRETER_TRANSLATE(vnmla),
INTERPRETER_TRANSLATE(vnmls),
INTERPRETER_TRANSLATE(vnmul),
INTERPRETER_TRANSLATE(vmul),
@@ -3548,6 +3507,7 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
CITRA_IGNORE_EXIT(-1);
}
inst_base = arm_instruction_trans[idx](inst, idx);
+
translated:
phys_addr += inst_size;
@@ -3580,6 +3540,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
Common::Profiling::ScopeTimer timer_execute(profile_execute);
MICROPROFILE_SCOPE(DynCom_Execute);
+ GDBStub::BreakpointAddress breakpoint_data;
+
#undef RM
#undef RS
@@ -3604,224 +3566,235 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
#define INC_PC(l) ptr += sizeof(arm_inst) + l
#define INC_PC_STUB ptr += sizeof(arm_inst)
+#define GDB_BP_CHECK \
+ cpu->Cpsr &= ~(1 << 5); \
+ cpu->Cpsr |= cpu->TFlag << 5; \
+ if (GDBStub::g_server_enabled) { \
+ if (GDBStub::IsMemoryBreak() || (breakpoint_data.type != GDBStub::BreakpointType::None && PC == breakpoint_data.address)) { \
+ GDBStub::Break(); \
+ goto END; \
+ } \
+ }
+
// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
// clunky switch statement.
#if defined __GNUC__ || defined __clang__
#define GOTO_NEXT_INST \
+ GDB_BP_CHECK; \
if (num_instrs >= cpu->NumInstrsToExecute) goto END; \
num_instrs++; \
goto *InstLabel[inst_base->idx]
#else
#define GOTO_NEXT_INST \
+ GDB_BP_CHECK; \
if (num_instrs >= cpu->NumInstrsToExecute) goto END; \
num_instrs++; \
switch(inst_base->idx) { \
case 0: goto VMLA_INST; \
case 1: goto VMLS_INST; \
case 2: goto VNMLA_INST; \
- case 3: goto VNMLA_INST; \
- case 4: goto VNMLS_INST; \
- case 5: goto VNMUL_INST; \
- case 6: goto VMUL_INST; \
- case 7: goto VADD_INST; \
- case 8: goto VSUB_INST; \
- case 9: goto VDIV_INST; \
- case 10: goto VMOVI_INST; \
- case 11: goto VMOVR_INST; \
- case 12: goto VABS_INST; \
- case 13: goto VNEG_INST; \
- case 14: goto VSQRT_INST; \
- case 15: goto VCMP_INST; \
- case 16: goto VCMP2_INST; \
- case 17: goto VCVTBDS_INST; \
- case 18: goto VCVTBFF_INST; \
- case 19: goto VCVTBFI_INST; \
- case 20: goto VMOVBRS_INST; \
- case 21: goto VMSR_INST; \
- case 22: goto VMOVBRC_INST; \
- case 23: goto VMRS_INST; \
- case 24: goto VMOVBCR_INST; \
- case 25: goto VMOVBRRSS_INST; \
- case 26: goto VMOVBRRD_INST; \
- case 27: goto VSTR_INST; \
- case 28: goto VPUSH_INST; \
- case 29: goto VSTM_INST; \
- case 30: goto VPOP_INST; \
- case 31: goto VLDR_INST; \
- case 32: goto VLDM_INST ; \
- case 33: goto SRS_INST; \
- case 34: goto RFE_INST; \
- case 35: goto BKPT_INST; \
- case 36: goto BLX_INST; \
- case 37: goto CPS_INST; \
- case 38: goto PLD_INST; \
- case 39: goto SETEND_INST; \
- case 40: goto CLREX_INST; \
- case 41: goto REV16_INST; \
- case 42: goto USAD8_INST; \
- case 43: goto SXTB_INST; \
- case 44: goto UXTB_INST; \
- case 45: goto SXTH_INST; \
- case 46: goto SXTB16_INST; \
- case 47: goto UXTH_INST; \
- case 48: goto UXTB16_INST; \
- case 49: goto CPY_INST; \
- case 50: goto UXTAB_INST; \
- case 51: goto SSUB8_INST; \
- case 52: goto SHSUB8_INST; \
- case 53: goto SSUBADDX_INST; \
- case 54: goto STREX_INST; \
- case 55: goto STREXB_INST; \
- case 56: goto SWP_INST; \
- case 57: goto SWPB_INST; \
- case 58: goto SSUB16_INST; \
- case 59: goto SSAT16_INST; \
- case 60: goto SHSUBADDX_INST; \
- case 61: goto QSUBADDX_INST; \
- case 62: goto SHADDSUBX_INST; \
- case 63: goto SHADD8_INST; \
- case 64: goto SHADD16_INST; \
- case 65: goto SEL_INST; \
- case 66: goto SADDSUBX_INST; \
- case 67: goto SADD8_INST; \
- case 68: goto SADD16_INST; \
- case 69: goto SHSUB16_INST; \
- case 70: goto UMAAL_INST; \
- case 71: goto UXTAB16_INST; \
- case 72: goto USUBADDX_INST; \
- case 73: goto USUB8_INST; \
- case 74: goto USUB16_INST; \
- case 75: goto USAT16_INST; \
- case 76: goto USADA8_INST; \
- case 77: goto UQSUBADDX_INST; \
- case 78: goto UQSUB8_INST; \
- case 79: goto UQSUB16_INST; \
- case 80: goto UQADDSUBX_INST; \
- case 81: goto UQADD8_INST; \
- case 82: goto UQADD16_INST; \
- case 83: goto SXTAB_INST; \
- case 84: goto UHSUBADDX_INST; \
- case 85: goto UHSUB8_INST; \
- case 86: goto UHSUB16_INST; \
- case 87: goto UHADDSUBX_INST; \
- case 88: goto UHADD8_INST; \
- case 89: goto UHADD16_INST; \
- case 90: goto UADDSUBX_INST; \
- case 91: goto UADD8_INST; \
- case 92: goto UADD16_INST; \
- case 93: goto SXTAH_INST; \
- case 94: goto SXTAB16_INST; \
- case 95: goto QADD8_INST; \
- case 96: goto BXJ_INST; \
- case 97: goto CLZ_INST; \
- case 98: goto UXTAH_INST; \
- case 99: goto BX_INST; \
- case 100: goto REV_INST; \
- case 101: goto BLX_INST; \
- case 102: goto REVSH_INST; \
- case 103: goto QADD_INST; \
- case 104: goto QADD16_INST; \
- case 105: goto QADDSUBX_INST; \
- case 106: goto LDREX_INST; \
- case 107: goto QDADD_INST; \
- case 108: goto QDSUB_INST; \
- case 109: goto QSUB_INST; \
- case 110: goto LDREXB_INST; \
- case 111: goto QSUB8_INST; \
- case 112: goto QSUB16_INST; \
- case 113: goto SMUAD_INST; \
- case 114: goto SMMUL_INST; \
- case 115: goto SMUSD_INST; \
- case 116: goto SMLSD_INST; \
- case 117: goto SMLSLD_INST; \
- case 118: goto SMMLA_INST; \
- case 119: goto SMMLS_INST; \
- case 120: goto SMLALD_INST; \
- case 121: goto SMLAD_INST; \
- case 122: goto SMLAW_INST; \
- case 123: goto SMULW_INST; \
- case 124: goto PKHTB_INST; \
- case 125: goto PKHBT_INST; \
- case 126: goto SMUL_INST; \
- case 127: goto SMLALXY_INST; \
- case 128: goto SMLA_INST; \
- case 129: goto MCRR_INST; \
- case 130: goto MRRC_INST; \
- case 131: goto CMP_INST; \
- case 132: goto TST_INST; \
- case 133: goto TEQ_INST; \
- case 134: goto CMN_INST; \
- case 135: goto SMULL_INST; \
- case 136: goto UMULL_INST; \
- case 137: goto UMLAL_INST; \
- case 138: goto SMLAL_INST; \
- case 139: goto MUL_INST; \
- case 140: goto MLA_INST; \
- case 141: goto SSAT_INST; \
- case 142: goto USAT_INST; \
- case 143: goto MRS_INST; \
- case 144: goto MSR_INST; \
- case 145: goto AND_INST; \
- case 146: goto BIC_INST; \
- case 147: goto LDM_INST; \
- case 148: goto EOR_INST; \
- case 149: goto ADD_INST; \
- case 150: goto RSB_INST; \
- case 151: goto RSC_INST; \
- case 152: goto SBC_INST; \
- case 153: goto ADC_INST; \
- case 154: goto SUB_INST; \
- case 155: goto ORR_INST; \
- case 156: goto MVN_INST; \
- case 157: goto MOV_INST; \
- case 158: goto STM_INST; \
- case 159: goto LDM_INST; \
- case 160: goto LDRSH_INST; \
- case 161: goto STM_INST; \
- case 162: goto LDM_INST; \
- case 163: goto LDRSB_INST; \
- case 164: goto STRD_INST; \
- case 165: goto LDRH_INST; \
- case 166: goto STRH_INST; \
- case 167: goto LDRD_INST; \
- case 168: goto STRT_INST; \
- case 169: goto STRBT_INST; \
- case 170: goto LDRBT_INST; \
- case 171: goto LDRT_INST; \
- case 172: goto MRC_INST; \
- case 173: goto MCR_INST; \
+ case 3: goto VNMLS_INST; \
+ case 4: goto VNMUL_INST; \
+ case 5: goto VMUL_INST; \
+ case 6: goto VADD_INST; \
+ case 7: goto VSUB_INST; \
+ case 8: goto VDIV_INST; \
+ case 9: goto VMOVI_INST; \
+ case 10: goto VMOVR_INST; \
+ case 11: goto VABS_INST; \
+ case 12: goto VNEG_INST; \
+ case 13: goto VSQRT_INST; \
+ case 14: goto VCMP_INST; \
+ case 15: goto VCMP2_INST; \
+ case 16: goto VCVTBDS_INST; \
+ case 17: goto VCVTBFF_INST; \
+ case 18: goto VCVTBFI_INST; \
+ case 19: goto VMOVBRS_INST; \
+ case 20: goto VMSR_INST; \
+ case 21: goto VMOVBRC_INST; \
+ case 22: goto VMRS_INST; \
+ case 23: goto VMOVBCR_INST; \
+ case 24: goto VMOVBRRSS_INST; \
+ case 25: goto VMOVBRRD_INST; \
+ case 26: goto VSTR_INST; \
+ case 27: goto VPUSH_INST; \
+ case 28: goto VSTM_INST; \
+ case 29: goto VPOP_INST; \
+ case 30: goto VLDR_INST; \
+ case 31: goto VLDM_INST ; \
+ case 32: goto SRS_INST; \
+ case 33: goto RFE_INST; \
+ case 34: goto BKPT_INST; \
+ case 35: goto BLX_INST; \
+ case 36: goto CPS_INST; \
+ case 37: goto PLD_INST; \
+ case 38: goto SETEND_INST; \
+ case 39: goto CLREX_INST; \
+ case 40: goto REV16_INST; \
+ case 41: goto USAD8_INST; \
+ case 42: goto SXTB_INST; \
+ case 43: goto UXTB_INST; \
+ case 44: goto SXTH_INST; \
+ case 45: goto SXTB16_INST; \
+ case 46: goto UXTH_INST; \
+ case 47: goto UXTB16_INST; \
+ case 48: goto CPY_INST; \
+ case 49: goto UXTAB_INST; \
+ case 50: goto SSUB8_INST; \
+ case 51: goto SHSUB8_INST; \
+ case 52: goto SSUBADDX_INST; \
+ case 53: goto STREX_INST; \
+ case 54: goto STREXB_INST; \
+ case 55: goto SWP_INST; \
+ case 56: goto SWPB_INST; \
+ case 57: goto SSUB16_INST; \
+ case 58: goto SSAT16_INST; \
+ case 59: goto SHSUBADDX_INST; \
+ case 60: goto QSUBADDX_INST; \
+ case 61: goto SHADDSUBX_INST; \
+ case 62: goto SHADD8_INST; \
+ case 63: goto SHADD16_INST; \
+ case 64: goto SEL_INST; \
+ case 65: goto SADDSUBX_INST; \
+ case 66: goto SADD8_INST; \
+ case 67: goto SADD16_INST; \
+ case 68: goto SHSUB16_INST; \
+ case 69: goto UMAAL_INST; \
+ case 70: goto UXTAB16_INST; \
+ case 71: goto USUBADDX_INST; \
+ case 72: goto USUB8_INST; \
+ case 73: goto USUB16_INST; \
+ case 74: goto USAT16_INST; \
+ case 75: goto USADA8_INST; \
+ case 76: goto UQSUBADDX_INST; \
+ case 77: goto UQSUB8_INST; \
+ case 78: goto UQSUB16_INST; \
+ case 79: goto UQADDSUBX_INST; \
+ case 80: goto UQADD8_INST; \
+ case 81: goto UQADD16_INST; \
+ case 82: goto SXTAB_INST; \
+ case 83: goto UHSUBADDX_INST; \
+ case 84: goto UHSUB8_INST; \
+ case 85: goto UHSUB16_INST; \
+ case 86: goto UHADDSUBX_INST; \
+ case 87: goto UHADD8_INST; \
+ case 88: goto UHADD16_INST; \
+ case 89: goto UADDSUBX_INST; \
+ case 90: goto UADD8_INST; \
+ case 91: goto UADD16_INST; \
+ case 92: goto SXTAH_INST; \
+ case 93: goto SXTAB16_INST; \
+ case 94: goto QADD8_INST; \
+ case 95: goto BXJ_INST; \
+ case 96: goto CLZ_INST; \
+ case 97: goto UXTAH_INST; \
+ case 98: goto BX_INST; \
+ case 99: goto REV_INST; \
+ case 100: goto BLX_INST; \
+ case 101: goto REVSH_INST; \
+ case 102: goto QADD_INST; \
+ case 103: goto QADD16_INST; \
+ case 104: goto QADDSUBX_INST; \
+ case 105: goto LDREX_INST; \
+ case 106: goto QDADD_INST; \
+ case 107: goto QDSUB_INST; \
+ case 108: goto QSUB_INST; \
+ case 109: goto LDREXB_INST; \
+ case 110: goto QSUB8_INST; \
+ case 111: goto QSUB16_INST; \
+ case 112: goto SMUAD_INST; \
+ case 113: goto SMMUL_INST; \
+ case 114: goto SMUSD_INST; \
+ case 115: goto SMLSD_INST; \
+ case 116: goto SMLSLD_INST; \
+ case 117: goto SMMLA_INST; \
+ case 118: goto SMMLS_INST; \
+ case 119: goto SMLALD_INST; \
+ case 120: goto SMLAD_INST; \
+ case 121: goto SMLAW_INST; \
+ case 122: goto SMULW_INST; \
+ case 123: goto PKHTB_INST; \
+ case 124: goto PKHBT_INST; \
+ case 125: goto SMUL_INST; \
+ case 126: goto SMLALXY_INST; \
+ case 127: goto SMLA_INST; \
+ case 128: goto MCRR_INST; \
+ case 129: goto MRRC_INST; \
+ case 130: goto CMP_INST; \
+ case 131: goto TST_INST; \
+ case 132: goto TEQ_INST; \
+ case 133: goto CMN_INST; \
+ case 134: goto SMULL_INST; \
+ case 135: goto UMULL_INST; \
+ case 136: goto UMLAL_INST; \
+ case 137: goto SMLAL_INST; \
+ case 138: goto MUL_INST; \
+ case 139: goto MLA_INST; \
+ case 140: goto SSAT_INST; \
+ case 141: goto USAT_INST; \
+ case 142: goto MRS_INST; \
+ case 143: goto MSR_INST; \
+ case 144: goto AND_INST; \
+ case 145: goto BIC_INST; \
+ case 146: goto LDM_INST; \
+ case 147: goto EOR_INST; \
+ case 148: goto ADD_INST; \
+ case 149: goto RSB_INST; \
+ case 150: goto RSC_INST; \
+ case 151: goto SBC_INST; \
+ case 152: goto ADC_INST; \
+ case 153: goto SUB_INST; \
+ case 154: goto ORR_INST; \
+ case 155: goto MVN_INST; \
+ case 156: goto MOV_INST; \
+ case 157: goto STM_INST; \
+ case 158: goto LDM_INST; \
+ case 159: goto LDRSH_INST; \
+ case 160: goto STM_INST; \
+ case 161: goto LDM_INST; \
+ case 162: goto LDRSB_INST; \
+ case 163: goto STRD_INST; \
+ case 164: goto LDRH_INST; \
+ case 165: goto STRH_INST; \
+ case 166: goto LDRD_INST; \
+ case 167: goto STRT_INST; \
+ case 168: goto STRBT_INST; \
+ case 169: goto LDRBT_INST; \
+ case 170: goto LDRT_INST; \
+ case 171: goto MRC_INST; \
+ case 172: goto MCR_INST; \
+ case 173: goto MSR_INST; \
case 174: goto MSR_INST; \
case 175: goto MSR_INST; \
case 176: goto MSR_INST; \
case 177: goto MSR_INST; \
- case 178: goto MSR_INST; \
- case 179: goto LDRB_INST; \
- case 180: goto STRB_INST; \
- case 181: goto LDR_INST; \
- case 182: goto LDRCOND_INST ; \
- case 183: goto STR_INST; \
- case 184: goto CDP_INST; \
- case 185: goto STC_INST; \
- case 186: goto LDC_INST; \
- case 187: goto LDREXD_INST; \
- case 188: goto STREXD_INST; \
- case 189: goto LDREXH_INST; \
- case 190: goto STREXH_INST; \
- case 191: goto NOP_INST; \
- case 192: goto YIELD_INST; \
- case 193: goto WFE_INST; \
- case 194: goto WFI_INST; \
- case 195: goto SEV_INST; \
- case 196: goto SWI_INST; \
- case 197: goto BBL_INST; \
- case 198: goto B_2_THUMB ; \
- case 199: goto B_COND_THUMB ; \
- case 200: goto BL_1_THUMB ; \
- case 201: goto BL_2_THUMB ; \
- case 202: goto BLX_1_THUMB ; \
- case 203: goto DISPATCH; \
- case 204: goto INIT_INST_LENGTH; \
- case 205: goto END; \
+ case 178: goto LDRB_INST; \
+ case 179: goto STRB_INST; \
+ case 180: goto LDR_INST; \
+ case 181: goto LDRCOND_INST ; \
+ case 182: goto STR_INST; \
+ case 183: goto CDP_INST; \
+ case 184: goto STC_INST; \
+ case 185: goto LDC_INST; \
+ case 186: goto LDREXD_INST; \
+ case 187: goto STREXD_INST; \
+ case 188: goto LDREXH_INST; \
+ case 189: goto STREXH_INST; \
+ case 190: goto NOP_INST; \
+ case 191: goto YIELD_INST; \
+ case 192: goto WFE_INST; \
+ case 193: goto WFI_INST; \
+ case 194: goto SEV_INST; \
+ case 195: goto SWI_INST; \
+ case 196: goto BBL_INST; \
+ case 197: goto B_2_THUMB ; \
+ case 198: goto B_COND_THUMB ; \
+ case 199: goto BL_1_THUMB ; \
+ case 200: goto BL_2_THUMB ; \
+ case 201: goto BLX_1_THUMB ; \
+ case 202: goto DISPATCH; \
+ case 203: goto INIT_INST_LENGTH; \
+ case 204: goto END; \
}
#endif
@@ -3848,7 +3821,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
// to a clunky switch statement.
#if defined __GNUC__ || defined __clang__
void *InstLabel[] = {
- &&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST,
+ &&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST,
&&VDIV_INST, &&VMOVI_INST, &&VMOVR_INST, &&VABS_INST, &&VNEG_INST, &&VSQRT_INST, &&VCMP_INST, &&VCMP2_INST, &&VCVTBDS_INST,
&&VCVTBFF_INST, &&VCVTBFI_INST, &&VMOVBRS_INST, &&VMSR_INST, &&VMOVBRC_INST, &&VMRS_INST, &&VMOVBCR_INST, &&VMOVBRRSS_INST,
&&VMOVBRRD_INST, &&VSTR_INST, &&VPUSH_INST, &&VSTM_INST, &&VPOP_INST, &&VLDR_INST, &&VLDM_INST,
@@ -3903,6 +3876,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
goto END;
}
+ // Find breakpoint if one exists within the block
+ if (GDBStub::g_server_enabled && GDBStub::IsConnected()) {
+ breakpoint_data = GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute);
+ }
+
inst_base = (arm_inst *)&inst_buf[ptr];
GOTO_NEXT_INST;
}
@@ -4454,12 +4432,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
-
- if (BITS(inst_cream->inst, 12, 15) == 15) {
- INC_PC(sizeof(ldst_inst));
- goto DISPATCH;
- }
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr);
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -4472,12 +4445,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
+ const u32 dest_index = BITS(inst_cream->inst, 12, 15);
+ const u32 previous_mode = cpu->Mode;
- if (BITS(inst_cream->inst, 12, 15) == 15) {
- INC_PC(sizeof(ldst_inst));
- goto DISPATCH;
- }
+ cpu->ChangePrivilegeMode(USER32MODE);
+ const u8 value = cpu->ReadMemory8(addr);
+ cpu->ChangePrivilegeMode(previous_mode);
+
+ cpu->Reg[dest_index] = value;
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -4513,10 +4488,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
cpu->SetExclusiveMemoryAddress(read_addr);
RD = cpu->ReadMemory32(read_addr);
- if (inst_cream->Rd == 15) {
- INC_PC(sizeof(generic_arm_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(generic_arm_inst));
@@ -4531,11 +4502,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
cpu->SetExclusiveMemoryAddress(read_addr);
- RD = Memory::Read8(read_addr);
- if (inst_cream->Rd == 15) {
- INC_PC(sizeof(generic_arm_inst));
- goto DISPATCH;
- }
+ RD = cpu->ReadMemory8(read_addr);
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(generic_arm_inst));
@@ -4551,10 +4518,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
cpu->SetExclusiveMemoryAddress(read_addr);
RD = cpu->ReadMemory16(read_addr);
- if (inst_cream->Rd == 15) {
- INC_PC(sizeof(generic_arm_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(generic_arm_inst));
@@ -4571,11 +4534,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
RD = cpu->ReadMemory32(read_addr);
RD2 = cpu->ReadMemory32(read_addr + 4);
-
- if (inst_cream->Rd == 15) {
- INC_PC(sizeof(generic_arm_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(generic_arm_inst));
@@ -4589,10 +4547,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
inst_cream->get_addr(cpu, inst_cream->inst, addr);
cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr);
- if (BITS(inst_cream->inst, 12, 15) == 15) {
- INC_PC(sizeof(ldst_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -4604,15 +4558,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
- unsigned int value = Memory::Read8(addr);
+ unsigned int value = cpu->ReadMemory8(addr);
if (BIT(value, 7)) {
value |= 0xffffff00;
}
cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- if (BITS(inst_cream->inst, 12, 15) == 15) {
- INC_PC(sizeof(ldst_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -4630,10 +4580,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
value |= 0xffff0000;
}
cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- if (BITS(inst_cream->inst, 12, 15) == 15) {
- INC_PC(sizeof(ldst_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -4646,13 +4592,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
- unsigned int value = cpu->ReadMemory32(addr);
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
+ const u32 dest_index = BITS(inst_cream->inst, 12, 15);
+ const u32 previous_mode = cpu->Mode;
- if (BITS(inst_cream->inst, 12, 15) == 15) {
- INC_PC(sizeof(ldst_inst));
- goto DISPATCH;
- }
+ cpu->ChangePrivilegeMode(USER32MODE);
+ const u32 value = cpu->ReadMemory32(addr);
+ cpu->ChangePrivilegeMode(previous_mode);
+
+ cpu->Reg[dest_index] = value;
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -4709,10 +4656,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
UPDATE_NFLAG(RD);
UPDATE_ZFLAG(RD);
}
- if (inst_cream->Rd == 15) {
- INC_PC(sizeof(mla_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(mla_inst));
@@ -4751,18 +4694,15 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
- unsigned int inst = inst_cream->inst;
- if (inst_cream->Rd == 15) {
- DEBUG_MSG;
- }
- if (inst_cream->inst == 0xeef04a10) {
- // Undefined instruction fmrx
- RD = 0x20000000;
- CITRA_IGNORE_EXIT(-1);
- goto END;
- } else {
- if (inst_cream->cp_num == 15)
- RD = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
+ if (inst_cream->cp_num == 15) {
+ const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
+
+ if (inst_cream->Rd == 15) {
+ cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000);
+ LOAD_NZCVT;
+ } else {
+ RD = value;
+ }
}
}
cpu->Reg[15] += cpu->GetInstructionSize();
@@ -4861,10 +4801,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
UPDATE_NFLAG(RD);
UPDATE_ZFLAG(RD);
}
- if (inst_cream->Rd == 15) {
- INC_PC(sizeof(mul_inst));
- goto DISPATCH;
- }
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(mul_inst));
@@ -6027,7 +5963,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
- Memory::Write8(addr, value);
+ cpu->WriteMemory8(addr, value);
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -6039,8 +5975,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
- unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
- Memory::Write8(addr, value);
+
+ const u32 previous_mode = cpu->Mode;
+ const u32 value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
+
+ cpu->ChangePrivilegeMode(USER32MODE);
+ cpu->WriteMemory8(addr, value);
+ cpu->ChangePrivilegeMode(previous_mode);
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -6091,7 +6032,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (cpu->IsExclusiveMemoryAccess(write_addr)) {
cpu->UnsetExclusiveMemoryAddress();
- Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]);
+ cpu->WriteMemory8(write_addr, cpu->Reg[inst_cream->Rm]);
RD = 0;
} else {
// Failed to write due to mutex access
@@ -6174,8 +6115,16 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
- unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
+ const u32 previous_mode = cpu->Mode;
+ const u32 rt_index = BITS(inst_cream->inst, 12, 15);
+
+ u32 value = cpu->Reg[rt_index];
+ if (rt_index == 15)
+ value += 2 * cpu->GetInstructionSize();
+
+ cpu->ChangePrivilegeMode(USER32MODE);
cpu->WriteMemory32(addr, value);
+ cpu->ChangePrivilegeMode(previous_mode);
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldst_inst));
@@ -6250,8 +6199,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
swp_inst* inst_cream = (swp_inst*)inst_base->component;
addr = RN;
- unsigned int value = Memory::Read8(addr);
- Memory::Write8(addr, (RM & 0xFF));
+ unsigned int value = cpu->ReadMemory8(addr);
+ cpu->WriteMemory8(addr, (RM & 0xFF));
RD = value;
}
cpu->Reg[15] += cpu->GetInstructionSize();
diff --git a/src/core/arm/dyncom/arm_dyncom_run.h b/src/core/arm/dyncom/arm_dyncom_run.h
index 13bef17fc..8eb694fee 100644
--- a/src/core/arm/dyncom/arm_dyncom_run.h
+++ b/src/core/arm/dyncom/arm_dyncom_run.h
@@ -30,7 +30,7 @@
* @return If the PC is being read, then the word-aligned PC value is returned.
* If the PC is not being read, then the value stored in the register is returned.
*/
-static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
+inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) {
return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
}
@@ -43,6 +43,6 @@ static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
* @return If the PC is being read, then the incremented PC value is returned.
* If the PC is not being read, then the values stored in the register is returned.
*/
-static inline u32 CHECK_READ_REG15(ARMul_State* cpu, int Rn) {
+inline u32 CHECK_READ_REG15(const ARMul_State* cpu, int Rn) {
return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
}
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h
index 447974363..c1be3c735 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.h
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.h
@@ -38,7 +38,7 @@ enum class ThumbDecodeStatus {
// Translates a Thumb mode instruction into its ARM equivalent.
ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size);
-static inline u32 GetThumbInstruction(u32 instr, u32 address) {
+inline u32 GetThumbInstruction(u32 instr, u32 address) {
// Normally you would need to handle instruction endianness,
// however, it is fixed to little-endian on the MPCore, so
// there's no need to check for this beforehand.
diff --git a/src/core/arm/skyeye_common/armstate.cpp b/src/core/arm/skyeye_common/armstate.cpp
index 0491717dc..2d814345a 100644
--- a/src/core/arm/skyeye_common/armstate.cpp
+++ b/src/core/arm/skyeye_common/armstate.cpp
@@ -7,6 +7,7 @@
#include "core/memory.h"
#include "core/arm/skyeye_common/armstate.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
+#include "core/gdbstub/gdbstub.h"
ARMul_State::ARMul_State(PrivilegeMode initial_mode)
{
@@ -185,8 +186,25 @@ void ARMul_State::ResetMPCoreCP15Registers()
CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
}
+static void CheckMemoryBreakpoint(u32 address, GDBStub::BreakpointType type)
+{
+ if (GDBStub::g_server_enabled && GDBStub::CheckBreakpoint(address, type)) {
+ LOG_DEBUG(Debug, "Found memory breakpoint @ %08x", address);
+ GDBStub::Break(true);
+ }
+}
+
+u8 ARMul_State::ReadMemory8(u32 address) const
+{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
+
+ return Memory::Read8(address);
+}
+
u16 ARMul_State::ReadMemory16(u32 address) const
{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
+
u16 data = Memory::Read16(address);
if (InBigEndianMode())
@@ -197,6 +215,8 @@ u16 ARMul_State::ReadMemory16(u32 address) const
u32 ARMul_State::ReadMemory32(u32 address) const
{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
+
u32 data = Memory::Read32(address);
if (InBigEndianMode())
@@ -207,6 +227,8 @@ u32 ARMul_State::ReadMemory32(u32 address) const
u64 ARMul_State::ReadMemory64(u32 address) const
{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Read);
+
u64 data = Memory::Read64(address);
if (InBigEndianMode())
@@ -215,8 +237,17 @@ u64 ARMul_State::ReadMemory64(u32 address) const
return data;
}
+void ARMul_State::WriteMemory8(u32 address, u8 data)
+{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
+
+ Memory::Write8(address, data);
+}
+
void ARMul_State::WriteMemory16(u32 address, u16 data)
{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
+
if (InBigEndianMode())
data = Common::swap16(data);
@@ -225,6 +256,8 @@ void ARMul_State::WriteMemory16(u32 address, u16 data)
void ARMul_State::WriteMemory32(u32 address, u32 data)
{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
+
if (InBigEndianMode())
data = Common::swap32(data);
@@ -233,6 +266,8 @@ void ARMul_State::WriteMemory32(u32 address, u32 data)
void ARMul_State::WriteMemory64(u32 address, u64 data)
{
+ CheckMemoryBreakpoint(address, GDBStub::BreakpointType::Write);
+
if (InBigEndianMode())
data = Common::swap64(data);
diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h
index ceb159d14..d42ff2669 100644
--- a/src/core/arm/skyeye_common/armstate.h
+++ b/src/core/arm/skyeye_common/armstate.h
@@ -153,9 +153,11 @@ public:
// Reads/writes data in big/little endian format based on the
// state of the E (endian) bit in the APSR.
+ u8 ReadMemory8(u32 address) const;
u16 ReadMemory16(u32 address) const;
u32 ReadMemory32(u32 address) const;
u64 ReadMemory64(u32 address) const;
+ void WriteMemory8(u32 address, u8 data);
void WriteMemory16(u32 address, u16 data);
void WriteMemory32(u32 address, u32 data);
void WriteMemory64(u32 address, u64 data);
@@ -191,23 +193,23 @@ public:
return TFlag ? 2 : 4;
}
- std::array<u32, 16> Reg; // The current register file
- std::array<u32, 2> Reg_usr;
- std::array<u32, 2> Reg_svc; // R13_SVC R14_SVC
- std::array<u32, 2> Reg_abort; // R13_ABORT R14_ABORT
- std::array<u32, 2> Reg_undef; // R13 UNDEF R14 UNDEF
- std::array<u32, 2> Reg_irq; // R13_IRQ R14_IRQ
- std::array<u32, 7> Reg_firq; // R8---R14 FIRQ
- std::array<u32, 7> Spsr; // The exception psr's
- std::array<u32, CP15_REGISTER_COUNT> CP15;
+ std::array<u32, 16> Reg{}; // The current register file
+ std::array<u32, 2> Reg_usr{};
+ std::array<u32, 2> Reg_svc{}; // R13_SVC R14_SVC
+ std::array<u32, 2> Reg_abort{}; // R13_ABORT R14_ABORT
+ std::array<u32, 2> Reg_undef{}; // R13 UNDEF R14 UNDEF
+ std::array<u32, 2> Reg_irq{}; // R13_IRQ R14_IRQ
+ std::array<u32, 7> Reg_firq{}; // R8---R14 FIRQ
+ std::array<u32, 7> Spsr{}; // The exception psr's
+ std::array<u32, CP15_REGISTER_COUNT> CP15{};
// FPSID, FPSCR, and FPEXC
- std::array<u32, VFP_SYSTEM_REGISTER_COUNT> VFP;
+ std::array<u32, VFP_SYSTEM_REGISTER_COUNT> VFP{};
// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
// and only 32 singleword registers are accessible (S0-S31).
- std::array<u32, 64> ExtReg;
+ std::array<u32, 64> ExtReg{};
u32 Emulate; // To start and stop emulation
u32 Cpsr; // The current PSR
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 0537135e2..a27a7e194 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -113,26 +113,26 @@ void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
/* Miscellaneous functions */
s32 vfp_get_float(ARMul_State* state, unsigned int reg)
{
- LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
+ LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]", reg, state->ExtReg[reg]);
return state->ExtReg[reg];
}
void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg)
{
- LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
+ LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]", reg, val);
state->ExtReg[reg] = val;
}
u64 vfp_get_double(ARMul_State* state, unsigned int reg)
{
u64 result = ((u64) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
- LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
+ LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]", reg * 2 + 1, reg * 2, result);
return result;
}
void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg)
{
- LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (u32)(val >> 32), (u32)(val & 0xffffffff));
+ LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2, (u32)(val >> 32), (u32)(val & 0xffffffff));
state->ExtReg[reg*2] = (u32) (val & 0xffffffff);
state->ExtReg[reg*2+1] = (u32) (val>>32);
}
@@ -142,10 +142,10 @@ void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg)
*/
void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x\n", exceptions);
+ LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x", exceptions);
if (exceptions == VFP_EXCEPTION_ERROR) {
- LOG_CRITICAL(Core_ARM11, "unhandled bounce %x\n", inst);
+ LOG_CRITICAL(Core_ARM11, "unhandled bounce %x", inst);
Crash();
}
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index 88908da9f..60a63e6de 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -22,7 +22,7 @@
#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
-#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested\n", __FUNCTION__);
+#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested", __FUNCTION__);
#define CHECK_VFP_ENABLED
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
diff --git a/src/core/arm/skyeye_common/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h
index 91a8d4d57..210972917 100644
--- a/src/core/arm/skyeye_common/vfp/vfp_helper.h
+++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h
@@ -85,7 +85,7 @@ enum : u32 {
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
-static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
+inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
{
if (shift) {
if (shift < 32)
@@ -96,7 +96,7 @@ static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
return val;
}
-static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
+inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
{
if (shift) {
if (shift < 64)
@@ -107,7 +107,7 @@ static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
return val;
}
-static inline u32 vfp_hi64to32jamming(u64 val)
+inline u32 vfp_hi64to32jamming(u64 val)
{
u32 v;
u32 highval = val >> 32;
@@ -121,7 +121,7 @@ static inline u32 vfp_hi64to32jamming(u64 val)
return v;
}
-static inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
+inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
{
*resl = nl + ml;
*resh = nh + mh;
@@ -129,7 +129,7 @@ static inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
*resh += 1;
}
-static inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
+inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
{
*resl = nl - ml;
*resh = nh - mh;
@@ -137,7 +137,7 @@ static inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
*resh -= 1;
}
-static inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
+inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
{
u32 nh, nl, mh, ml;
u64 rh, rma, rmb, rl;
@@ -164,20 +164,20 @@ static inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
*resh = rh;
}
-static inline void shift64left(u64* resh, u64* resl, u64 n)
+inline void shift64left(u64* resh, u64* resl, u64 n)
{
*resh = n >> 63;
*resl = n << 1;
}
-static inline u64 vfp_hi64multiply64(u64 n, u64 m)
+inline u64 vfp_hi64multiply64(u64 n, u64 m)
{
u64 rh, rl;
mul64to128(&rh, &rl, n, m);
return rh | (rl != 0);
}
-static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
+inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
{
u64 mh, ml, remh, reml, termh, terml, z;
@@ -249,7 +249,7 @@ enum : u32 {
VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
};
-static inline int vfp_single_type(vfp_single* s)
+inline int vfp_single_type(const vfp_single* s)
{
int type = VFP_NUMBER;
if (s->exponent == 255) {
@@ -271,7 +271,7 @@ static inline int vfp_single_type(vfp_single* s)
// Unpack a single-precision float. Note that this returns the magnitude
// of the single-precision float mantissa with the 1. if necessary,
// aligned to bit 30.
-static inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
+inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
{
s->sign = vfp_single_packed_sign(val) >> 16,
s->exponent = vfp_single_packed_exponent(val);
@@ -293,7 +293,7 @@ static inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
// Re-pack a single-precision float. This assumes that the float is
// already normalised such that the MSB is bit 30, _not_ bit 31.
-static inline s32 vfp_single_pack(vfp_single* s)
+inline s32 vfp_single_pack(const vfp_single* s)
{
u32 val = (s->sign << 16) +
(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
@@ -335,7 +335,7 @@ struct vfp_double {
#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
-static inline int vfp_double_type(vfp_double* s)
+inline int vfp_double_type(const vfp_double* s)
{
int type = VFP_NUMBER;
if (s->exponent == 2047) {
@@ -357,7 +357,7 @@ static inline int vfp_double_type(vfp_double* s)
// Unpack a double-precision float. Note that this returns the magnitude
// of the double-precision float mantissa with the 1. if necessary,
// aligned to bit 62.
-static inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
+inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
{
s->sign = vfp_double_packed_sign(val) >> 48;
s->exponent = vfp_double_packed_exponent(val);
@@ -379,7 +379,7 @@ static inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
// Re-pack a double-precision float. This assumes that the float is
// already normalised such that the MSB is bit 30, _not_ bit 31.
-static inline s64 vfp_double_pack(vfp_double* s)
+inline s64 vfp_double_pack(const vfp_double* s)
{
u64 val = ((u64)s->sign << 48) +
((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
@@ -415,7 +415,7 @@ struct op {
u32 flags;
};
-static inline u32 fls(u32 x)
+inline u32 fls(u32 x)
{
int r = 32;
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index 857e6ce45..45914d479 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -65,7 +65,7 @@ static struct vfp_double vfp_double_default_qnan = {
static void vfp_double_dump(const char *str, struct vfp_double *d)
{
- LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx\n",
+ LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx",
str, d->sign != 0, d->exponent, d->significand);
}
@@ -155,7 +155,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
} else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
- LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
+ LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx", incr);
/*
* Is our rounding going to overflow?
@@ -210,7 +210,7 @@ pack:
vfp_double_dump("pack: final", vd);
{
s64 d = vfp_double_pack(vd);
- LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func,
+ LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func,
dd, d, exceptions);
vfp_put_double(state, d, dd);
}
@@ -267,28 +267,28 @@ vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn,
*/
static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd);
return 0;
}
static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_put_double(state, vfp_get_double(state, dm), dd);
return 0;
}
static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd);
return 0;
}
static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double vdm, vdd, *vdp;
int ret, tm;
@@ -383,7 +383,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
s64 d, m;
u32 ret = 0;
- LOG_TRACE(Core_ARM11, "In %s, state=0x%p, fpscr=0x%x\n", __FUNCTION__, state, fpscr);
+ LOG_TRACE(Core_ARM11, "In %s, state=0x%p, fpscr=0x%x", __FUNCTION__, state, fpscr);
m = vfp_get_double(state, dm);
if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
ret |= FPSCR_CFLAG | FPSCR_VFLAG;
@@ -438,32 +438,32 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
ret |= FPSCR_CFLAG;
}
}
- LOG_TRACE(Core_ARM11, "In %s, state=0x%p, ret=0x%x\n", __FUNCTION__, state, ret);
+ LOG_TRACE(Core_ARM11, "In %s, state=0x%p, ret=0x%x", __FUNCTION__, state, ret);
return ret;
}
static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_compare(state, dd, 0, dm, fpscr);
}
static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_compare(state, dd, 1, dm, fpscr);
}
static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr);
}
static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
}
@@ -474,7 +474,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32
int tm;
u32 exceptions = 0;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm), &fpscr);
tm = vfp_double_type(&vdm);
@@ -516,7 +516,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32
struct vfp_double vdm;
u32 m = vfp_get_float(state, dm);
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vdm.sign = 0;
vdm.exponent = 1023 + 63 - 1;
vdm.significand = (u64)m;
@@ -529,7 +529,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32
struct vfp_double vdm;
u32 m = vfp_get_float(state, dm);
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vdm.sign = (m & 0x80000000) >> 16;
vdm.exponent = 1023 + 63 - 1;
vdm.significand = vdm.sign ? (~m + 1) : m;
@@ -544,7 +544,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
int rmode = fpscr & FPSCR_RMODE_MASK;
int tm;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm), &fpscr);
/*
@@ -605,7 +605,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
}
}
- LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
+ LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
vfp_put_float(state, d, sd);
@@ -614,7 +614,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_double_ftoui(state, sd, unused, dm, FPSCR_ROUND_TOZERO);
}
@@ -625,7 +625,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
int rmode = fpscr & FPSCR_RMODE_MASK;
int tm;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm), &fpscr);
vfp_double_dump("VDM", &vdm);
@@ -682,7 +682,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
}
}
- LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
+ LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
vfp_put_float(state, (s32)d, sd);
@@ -691,7 +691,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_double_ftosi(state, dd, unused, dm, FPSCR_ROUND_TOZERO);
}
@@ -775,7 +775,7 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou
if (vdn->significand & (1ULL << 63) ||
vdm->significand & (1ULL << 63)) {
- LOG_INFO(Core_ARM11, "VFP: bad FP values in %s\n", __func__);
+ LOG_INFO(Core_ARM11, "VFP: bad FP values in %s", __func__);
vfp_double_dump("VDN", vdn);
vfp_double_dump("VDM", vdm);
}
@@ -843,7 +843,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
*/
if (vdn->exponent < vdm->exponent) {
std::swap(vdm, vdn);
- LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N\n");
+ LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N");
}
vdd->sign = vdn->sign ^ vdm->sign;
@@ -927,7 +927,7 @@ vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 f
*/
static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac");
}
@@ -936,7 +936,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
*/
static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac");
}
@@ -945,7 +945,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
*/
static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc");
}
@@ -954,7 +954,7 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
*/
static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc");
}
@@ -966,7 +966,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn), &fpscr);
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -987,7 +987,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn), &fpscr);
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1010,7 +1010,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn), &fpscr);
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1032,7 +1032,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn), &fpscr);
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1060,7 +1060,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
u32 exceptions = 0;
int tm, tn;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn), &fpscr);
vfp_double_unpack(&vdm, vfp_get_double(state, dm), &fpscr);
@@ -1185,7 +1185,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
unsigned int vecitr, veclen, vecstride;
struct op *fop;
- LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
@@ -1216,7 +1216,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
else
veclen = fpscr & FPSCR_LENGTH_MASK;
- LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u\n", vecstride,
+ LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u", vecstride,
(veclen >> FPSCR_LENGTH_BIT) + 1);
if (!fop->fn) {
@@ -1230,16 +1230,16 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
type = (fop->flags & OP_SD) ? 's' : 'd';
if (op == FOP_EXT)
- LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)\n",
+ LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)",
vecitr >> FPSCR_LENGTH_BIT,
type, dest, dn, dm);
else
- LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
+ LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)",
vecitr >> FPSCR_LENGTH_BIT,
type, dest, dn, FOP_TO_IDX(op), dm);
except = fop->fn(state, dest, dn, dm, fpscr);
- LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x\n",
+ LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x",
vecitr >> FPSCR_LENGTH_BIT, except);
exceptions |= except;
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-29 04:40:40 +0000