aboutsummaryrefslogtreecommitdiff
path: root/src/core/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h5
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.cpp59
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.h14
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp61
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.h10
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_cp15.h2
-rw-r--r--src/core/arm/dynarmic/arm_exclusive_monitor.h2
7 files changed, 84 insertions, 69 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 9a0151736..689e3ceb5 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -65,9 +65,6 @@ public:
/// Step CPU by one instruction
virtual void Step() = 0;
- /// Exits execution from a callback, the callback must rewind the stack
- virtual void ExceptionalExit() = 0;
-
/// Clear all instruction cache
virtual void ClearInstructionCache() = 0;
@@ -159,8 +156,6 @@ public:
*/
virtual void SetTPIDR_EL0(u64 value) = 0;
- virtual void ChangeProcessorID(std::size_t new_core_id) = 0;
-
virtual void SaveContext(ThreadContext32& ctx) = 0;
virtual void SaveContext(ThreadContext64& ctx) = 0;
virtual void LoadContext(const ThreadContext32& ctx) = 0;
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 93d43e22e..cea7f0fb1 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -4,9 +4,9 @@
#include <cinttypes>
#include <memory>
-#include <dynarmic/A32/a32.h>
-#include <dynarmic/A32/config.h>
-#include <dynarmic/A32/context.h>
+#include <dynarmic/interface/A32/a32.h>
+#include <dynarmic/interface/A32/config.h>
+#include <dynarmic/interface/A32/context.h>
#include "common/assert.h"
#include "common/logging/log.h"
#include "common/page_table.h"
@@ -24,45 +24,46 @@ namespace Core {
class DynarmicCallbacks32 : public Dynarmic::A32::UserCallbacks {
public:
- explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent_) : parent{parent_} {}
+ explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent_)
+ : parent{parent_}, memory(parent.system.Memory()) {}
u8 MemoryRead8(u32 vaddr) override {
- return parent.system.Memory().Read8(vaddr);
+ return memory.Read8(vaddr);
}
u16 MemoryRead16(u32 vaddr) override {
- return parent.system.Memory().Read16(vaddr);
+ return memory.Read16(vaddr);
}
u32 MemoryRead32(u32 vaddr) override {
- return parent.system.Memory().Read32(vaddr);
+ return memory.Read32(vaddr);
}
u64 MemoryRead64(u32 vaddr) override {
- return parent.system.Memory().Read64(vaddr);
+ return memory.Read64(vaddr);
}
void MemoryWrite8(u32 vaddr, u8 value) override {
- parent.system.Memory().Write8(vaddr, value);
+ memory.Write8(vaddr, value);
}
void MemoryWrite16(u32 vaddr, u16 value) override {
- parent.system.Memory().Write16(vaddr, value);
+ memory.Write16(vaddr, value);
}
void MemoryWrite32(u32 vaddr, u32 value) override {
- parent.system.Memory().Write32(vaddr, value);
+ memory.Write32(vaddr, value);
}
void MemoryWrite64(u32 vaddr, u64 value) override {
- parent.system.Memory().Write64(vaddr, value);
+ memory.Write64(vaddr, value);
}
bool MemoryWriteExclusive8(u32 vaddr, u8 value, u8 expected) override {
- return parent.system.Memory().WriteExclusive8(vaddr, value, expected);
+ return memory.WriteExclusive8(vaddr, value, expected);
}
bool MemoryWriteExclusive16(u32 vaddr, u16 value, u16 expected) override {
- return parent.system.Memory().WriteExclusive16(vaddr, value, expected);
+ return memory.WriteExclusive16(vaddr, value, expected);
}
bool MemoryWriteExclusive32(u32 vaddr, u32 value, u32 expected) override {
- return parent.system.Memory().WriteExclusive32(vaddr, value, expected);
+ return memory.WriteExclusive32(vaddr, value, expected);
}
bool MemoryWriteExclusive64(u32 vaddr, u64 value, u64 expected) override {
- return parent.system.Memory().WriteExclusive64(vaddr, value, expected);
+ return memory.WriteExclusive64(vaddr, value, expected);
}
void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
@@ -78,7 +79,9 @@ public:
}
void CallSVC(u32 swi) override {
- Kernel::Svc::Call(parent.system, swi);
+ parent.svc_called = true;
+ parent.svc_swi = swi;
+ parent.jit->HaltExecution();
}
void AddTicks(u64 ticks) override {
@@ -110,6 +113,7 @@ public:
}
ARM_Dynarmic_32& parent;
+ Core::Memory::Memory& memory;
std::size_t num_interpreted_instructions{};
static constexpr u64 minimum_run_cycles = 1000U;
};
@@ -187,11 +191,17 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
}
void ARM_Dynarmic_32::Run() {
- jit->Run();
-}
-
-void ARM_Dynarmic_32::ExceptionalExit() {
- jit->ExceptionalExit();
+ while (true) {
+ jit->Run();
+ if (!svc_called) {
+ break;
+ }
+ svc_called = false;
+ Kernel::Svc::Call(system, svc_swi);
+ if (shutdown) {
+ break;
+ }
+ }
}
void ARM_Dynarmic_32::Step() {
@@ -255,10 +265,6 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
cp15->uprw = static_cast<u32>(value);
}
-void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) {
- jit->ChangeProcessorID(new_core_id);
-}
-
void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
Dynarmic::A32::Context context;
jit->SaveContext(context);
@@ -279,6 +285,7 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
void ARM_Dynarmic_32::PrepareReschedule() {
jit->HaltExecution();
+ shutdown = true;
}
void ARM_Dynarmic_32::ClearInstructionCache() {
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h
index 42778c02c..063605b46 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.h
@@ -7,9 +7,9 @@
#include <memory>
#include <unordered_map>
-#include <dynarmic/A32/a32.h>
-#include <dynarmic/A64/a64.h>
-#include <dynarmic/exclusive_monitor.h>
+#include <dynarmic/interface/A32/a32.h>
+#include <dynarmic/interface/A64/a64.h>
+#include <dynarmic/interface/exclusive_monitor.h>
#include "common/common_types.h"
#include "common/hash.h"
#include "core/arm/arm_interface.h"
@@ -42,13 +42,11 @@ public:
u32 GetPSTATE() const override;
void SetPSTATE(u32 pstate) override;
void Run() override;
- void ExceptionalExit() override;
void Step() override;
VAddr GetTlsAddress() const override;
void SetTlsAddress(VAddr address) override;
void SetTPIDR_EL0(u64 value) override;
u64 GetTPIDR_EL0() const override;
- void ChangeProcessorID(std::size_t new_core_id) override;
bool IsInThumbMode() const {
return (GetPSTATE() & 0x20) != 0;
@@ -83,6 +81,12 @@ private:
std::size_t core_index;
DynarmicExclusiveMonitor& exclusive_monitor;
std::shared_ptr<Dynarmic::A32::Jit> jit;
+
+ // SVC callback
+ u32 svc_swi{};
+ bool svc_called{};
+
+ bool shutdown{};
};
} // namespace Core
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 08fa85904..63193dcb1 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -4,8 +4,8 @@
#include <cinttypes>
#include <memory>
-#include <dynarmic/A64/a64.h>
-#include <dynarmic/A64/config.h>
+#include <dynarmic/interface/A64/a64.h>
+#include <dynarmic/interface/A64/config.h>
#include "common/assert.h"
#include "common/logging/log.h"
#include "common/page_table.h"
@@ -27,57 +27,56 @@ using Vector = Dynarmic::A64::Vector;
class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
public:
- explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent_) : parent{parent_} {}
+ explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent_)
+ : parent{parent_}, memory(parent.system.Memory()) {}
u8 MemoryRead8(u64 vaddr) override {
- return parent.system.Memory().Read8(vaddr);
+ return memory.Read8(vaddr);
}
u16 MemoryRead16(u64 vaddr) override {
- return parent.system.Memory().Read16(vaddr);
+ return memory.Read16(vaddr);
}
u32 MemoryRead32(u64 vaddr) override {
- return parent.system.Memory().Read32(vaddr);
+ return memory.Read32(vaddr);
}
u64 MemoryRead64(u64 vaddr) override {
- return parent.system.Memory().Read64(vaddr);
+ return memory.Read64(vaddr);
}
Vector MemoryRead128(u64 vaddr) override {
- auto& memory = parent.system.Memory();
return {memory.Read64(vaddr), memory.Read64(vaddr + 8)};
}
void MemoryWrite8(u64 vaddr, u8 value) override {
- parent.system.Memory().Write8(vaddr, value);
+ memory.Write8(vaddr, value);
}
void MemoryWrite16(u64 vaddr, u16 value) override {
- parent.system.Memory().Write16(vaddr, value);
+ memory.Write16(vaddr, value);
}
void MemoryWrite32(u64 vaddr, u32 value) override {
- parent.system.Memory().Write32(vaddr, value);
+ memory.Write32(vaddr, value);
}
void MemoryWrite64(u64 vaddr, u64 value) override {
- parent.system.Memory().Write64(vaddr, value);
+ memory.Write64(vaddr, value);
}
void MemoryWrite128(u64 vaddr, Vector value) override {
- auto& memory = parent.system.Memory();
memory.Write64(vaddr, value[0]);
memory.Write64(vaddr + 8, value[1]);
}
bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
- return parent.system.Memory().WriteExclusive8(vaddr, value, expected);
+ return memory.WriteExclusive8(vaddr, value, expected);
}
bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
- return parent.system.Memory().WriteExclusive16(vaddr, value, expected);
+ return memory.WriteExclusive16(vaddr, value, expected);
}
bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
- return parent.system.Memory().WriteExclusive32(vaddr, value, expected);
+ return memory.WriteExclusive32(vaddr, value, expected);
}
bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
- return parent.system.Memory().WriteExclusive64(vaddr, value, expected);
+ return memory.WriteExclusive64(vaddr, value, expected);
}
bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
- return parent.system.Memory().WriteExclusive128(vaddr, value, expected);
+ return memory.WriteExclusive128(vaddr, value, expected);
}
void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
@@ -102,7 +101,9 @@ public:
}
void CallSVC(u32 swi) override {
- Kernel::Svc::Call(parent.system, swi);
+ parent.svc_called = true;
+ parent.svc_swi = swi;
+ parent.jit->HaltExecution();
}
void AddTicks(u64 ticks) override {
@@ -137,6 +138,7 @@ public:
}
ARM_Dynarmic_64& parent;
+ Core::Memory::Memory& memory;
u64 tpidrro_el0 = 0;
u64 tpidr_el0 = 0;
static constexpr u64 minimum_run_cycles = 1000U;
@@ -227,11 +229,17 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
}
void ARM_Dynarmic_64::Run() {
- jit->Run();
-}
-
-void ARM_Dynarmic_64::ExceptionalExit() {
- jit->ExceptionalExit();
+ while (true) {
+ jit->Run();
+ if (!svc_called) {
+ break;
+ }
+ svc_called = false;
+ Kernel::Svc::Call(system, svc_swi);
+ if (shutdown) {
+ break;
+ }
+ }
}
void ARM_Dynarmic_64::Step() {
@@ -296,10 +304,6 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
cb->tpidr_el0 = value;
}
-void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) {
- jit->ChangeProcessorID(new_core_id);
-}
-
void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
ctx.cpu_registers = jit->GetRegisters();
ctx.sp = jit->GetSP();
@@ -324,6 +328,7 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
void ARM_Dynarmic_64::PrepareReschedule() {
jit->HaltExecution();
+ shutdown = true;
}
void ARM_Dynarmic_64::ClearInstructionCache() {
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h
index b81fbcc66..0c4e46c64 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.h
@@ -7,7 +7,7 @@
#include <memory>
#include <unordered_map>
-#include <dynarmic/A64/a64.h>
+#include <dynarmic/interface/A64/a64.h>
#include "common/common_types.h"
#include "common/hash.h"
#include "core/arm/arm_interface.h"
@@ -40,12 +40,10 @@ public:
void SetPSTATE(u32 pstate) override;
void Run() override;
void Step() override;
- void ExceptionalExit() override;
VAddr GetTlsAddress() const override;
void SetTlsAddress(VAddr address) override;
void SetTPIDR_EL0(u64 value) override;
u64 GetTPIDR_EL0() const override;
- void ChangeProcessorID(std::size_t new_core_id) override;
void SaveContext(ThreadContext32& ctx) override {}
void SaveContext(ThreadContext64& ctx) override;
@@ -76,6 +74,12 @@ private:
DynarmicExclusiveMonitor& exclusive_monitor;
std::shared_ptr<Dynarmic::A64::Jit> jit;
+
+ // SVC callback
+ u32 svc_swi{};
+ bool svc_called{};
+
+ bool shutdown{};
};
} // namespace Core
diff --git a/src/core/arm/dynarmic/arm_dynarmic_cp15.h b/src/core/arm/dynarmic/arm_dynarmic_cp15.h
index 8597beddf..7c7ede79e 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_cp15.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_cp15.h
@@ -7,7 +7,7 @@
#include <memory>
#include <optional>
-#include <dynarmic/A32/coprocessor.h>
+#include <dynarmic/interface/A32/coprocessor.h>
#include "common/common_types.h"
namespace Core {
diff --git a/src/core/arm/dynarmic/arm_exclusive_monitor.h b/src/core/arm/dynarmic/arm_exclusive_monitor.h
index f9f056a59..73d41f223 100644
--- a/src/core/arm/dynarmic/arm_exclusive_monitor.h
+++ b/src/core/arm/dynarmic/arm_exclusive_monitor.h
@@ -7,7 +7,7 @@
#include <memory>
#include <unordered_map>
-#include <dynarmic/exclusive_monitor.h>
+#include <dynarmic/interface/exclusive_monitor.h>
#include "common/common_types.h"
#include "core/arm/dynarmic/arm_dynarmic_32.h"
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-31 08:14:58 +0000