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-rw-r--r--src/core/arm/arm_interface.h33
-rw-r--r--src/core/arm/interpreter/arm_interpreter.cpp99
-rw-r--r--src/core/arm/interpreter/arm_interpreter.h23
-rw-r--r--src/core/arm/interpreter/armdefs.h4
-rw-r--r--src/core/arm/interpreter/armemu.cpp23
-rw-r--r--src/core/arm/interpreter/arminit.cpp3
-rw-r--r--src/core/arm/interpreter/vfp/vfp.h2
7 files changed, 134 insertions, 53 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 9fdc7ba3c..be677ae20 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -7,11 +7,13 @@
#include "common/common.h"
#include "common/common_types.h"
+#include "core/hle/svc.h"
+
/// Generic ARM11 CPU interface
class ARM_Interface : NonCopyable {
public:
ARM_Interface() {
- m_num_instructions = 0;
+ num_instructions = 0;
}
~ARM_Interface() {
@@ -23,7 +25,7 @@ public:
*/
void Run(int num_instructions) {
ExecuteInstructions(num_instructions);
- m_num_instructions += num_instructions;
+ this->num_instructions += num_instructions;
}
/// Step CPU by one instruction
@@ -64,14 +66,35 @@ public:
virtual u32 GetCPSR() const = 0;
/**
+ * Set the current CPSR register
+ * @param cpsr Value to set CPSR to
+ */
+ virtual void SetCPSR(u32 cpsr) = 0;
+
+ /**
* Returns the number of clock ticks since the last rese
* @return Returns number of clock ticks
*/
virtual u64 GetTicks() const = 0;
- /// Getter for m_num_instructions
+ /**
+ * Saves the current CPU context
+ * @param ctx Thread context to save
+ */
+ virtual void SaveContext(ThreadContext& ctx) = 0;
+
+ /**
+ * Loads a CPU context
+ * @param ctx Thread context to load
+ */
+ virtual void LoadContext(const ThreadContext& ctx) = 0;
+
+ /// Prepare core for thread reschedule (if needed to correctly handle state)
+ virtual void PrepareReschedule() = 0;
+
+ /// Getter for num_instructions
u64 GetNumInstructions() {
- return m_num_instructions;
+ return num_instructions;
}
protected:
@@ -84,6 +107,6 @@ protected:
private:
- u64 m_num_instructions; ///< Number of instructions executed
+ u64 num_instructions; ///< Number of instructions executed
};
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 23d96d292..0e893f182 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -9,30 +9,30 @@ const static cpu_config_t s_arm11_cpu_info = {
};
ARM_Interpreter::ARM_Interpreter() {
- m_state = new ARMul_State;
+ state = new ARMul_State;
ARMul_EmulateInit();
- ARMul_NewState(m_state);
+ ARMul_NewState(state);
- m_state->abort_model = 0;
- m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
- m_state->bigendSig = LOW;
+ state->abort_model = 0;
+ state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
+ state->bigendSig = LOW;
- ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
- m_state->lateabtSig = LOW;
- mmu_init(m_state);
+ ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
+ state->lateabtSig = LOW;
+ mmu_init(state);
// Reset the core to initial state
- ARMul_Reset(m_state);
- m_state->NextInstr = 0;
- m_state->Emulate = 3;
+ ARMul_Reset(state);
+ state->NextInstr = 0;
+ state->Emulate = 3;
- m_state->pc = m_state->Reg[15] = 0x00000000;
- m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
+ state->pc = state->Reg[15] = 0x00000000;
+ state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
}
ARM_Interpreter::~ARM_Interpreter() {
- delete m_state;
+ delete state;
}
/**
@@ -40,7 +40,7 @@ ARM_Interpreter::~ARM_Interpreter() {
* @param addr Address to set PC to
*/
void ARM_Interpreter::SetPC(u32 pc) {
- m_state->pc = m_state->Reg[15] = pc;
+ state->pc = state->Reg[15] = pc;
}
/*
@@ -48,7 +48,7 @@ void ARM_Interpreter::SetPC(u32 pc) {
* @return Returns current PC
*/
u32 ARM_Interpreter::GetPC() const {
- return m_state->pc;
+ return state->pc;
}
/**
@@ -57,7 +57,7 @@ u32 ARM_Interpreter::GetPC() const {
* @return Returns the value in the register
*/
u32 ARM_Interpreter::GetReg(int index) const {
- return m_state->Reg[index];
+ return state->Reg[index];
}
/**
@@ -66,7 +66,7 @@ u32 ARM_Interpreter::GetReg(int index) const {
* @param value Value to set register to
*/
void ARM_Interpreter::SetReg(int index, u32 value) {
- m_state->Reg[index] = value;
+ state->Reg[index] = value;
}
/**
@@ -74,7 +74,15 @@ void ARM_Interpreter::SetReg(int index, u32 value) {
* @return Returns the value of the CPSR register
*/
u32 ARM_Interpreter::GetCPSR() const {
- return m_state->Cpsr;
+ return state->Cpsr;
+}
+
+/**
+ * Set the current CPSR register
+ * @param cpsr Value to set CPSR to
+ */
+void ARM_Interpreter::SetCPSR(u32 cpsr) {
+ state->Cpsr = cpsr;
}
/**
@@ -82,7 +90,7 @@ u32 ARM_Interpreter::GetCPSR() const {
* @return Returns number of clock ticks
*/
u64 ARM_Interpreter::GetTicks() const {
- return ARMul_Time(m_state);
+ return ARMul_Time(state);
}
/**
@@ -90,6 +98,53 @@ u64 ARM_Interpreter::GetTicks() const {
* @param num_instructions Number of instructions to executes
*/
void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
- m_state->NumInstrsToExecute = num_instructions;
- ARMul_Emulate32(m_state);
+ state->NumInstrsToExecute = num_instructions - 1;
+ ARMul_Emulate32(state);
+}
+
+/**
+ * Saves the current CPU context
+ * @param ctx Thread context to save
+ * @todo Do we need to save Reg[15] and NextInstr?
+ */
+void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
+ memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
+ memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
+
+ ctx.sp = state->Reg[13];
+ ctx.lr = state->Reg[14];
+ ctx.pc = state->pc;
+ ctx.cpsr = state->Cpsr;
+
+ ctx.fpscr = state->VFP[1];
+ ctx.fpexc = state->VFP[2];
+
+ ctx.reg_15 = state->Reg[15];
+ ctx.mode = state->NextInstr;
+}
+
+/**
+ * Loads a CPU context
+ * @param ctx Thread context to load
+ * @param Do we need to load Reg[15] and NextInstr?
+ */
+void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
+ memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
+ memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
+
+ state->Reg[13] = ctx.sp;
+ state->Reg[14] = ctx.lr;
+ state->pc = ctx.pc;
+ state->Cpsr = ctx.cpsr;
+
+ state->VFP[1] = ctx.fpscr;
+ state->VFP[2] = ctx.fpexc;
+
+ state->Reg[15] = ctx.reg_15;
+ state->NextInstr = ctx.mode;
+}
+
+/// Prepare core for thread reschedule (if needed to correctly handle state)
+void ARM_Interpreter::PrepareReschedule() {
+ state->NumInstrsToExecute = 0;
}
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 509025080..1e82883a2 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -49,11 +49,32 @@ public:
u32 GetCPSR() const;
/**
+ * Set the current CPSR register
+ * @param cpsr Value to set CPSR to
+ */
+ void SetCPSR(u32 cpsr);
+
+ /**
* Returns the number of clock ticks since the last reset
* @return Returns number of clock ticks
*/
u64 GetTicks() const;
+ /**
+ * Saves the current CPU context
+ * @param ctx Thread context to save
+ */
+ void SaveContext(ThreadContext& ctx);
+
+ /**
+ * Loads a CPU context
+ * @param ctx Thread context to load
+ */
+ void LoadContext(const ThreadContext& ctx);
+
+ /// Prepare core for thread reschedule (if needed to correctly handle state)
+ void PrepareReschedule();
+
protected:
/**
@@ -64,6 +85,6 @@ protected:
private:
- ARMul_State* m_state;
+ ARMul_State* state;
};
diff --git a/src/core/arm/interpreter/armdefs.h b/src/core/arm/interpreter/armdefs.h
index 5b2abc7f7..d8eae4d3f 100644
--- a/src/core/arm/interpreter/armdefs.h
+++ b/src/core/arm/interpreter/armdefs.h
@@ -24,10 +24,6 @@
#include "common/platform.h"
-#if EMU_PLATFORM == PLATFORM_WINDOWS
-#include <windows.h>
-#endif
-
//teawater add for arm2x86 2005.02.14-------------------------------------------
// koodailar remove it for mingw 2005.12.18----------------
//anthonylee modify it for portable 2007.01.30
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 32e315f4b..f3c14e608 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -4456,6 +4456,7 @@ ARMul_Emulate26 (ARMul_State * state)
}
/* Drop through. */
+ case 0xe0:
case 0xe4:
case 0xe6:
case 0xe8:
@@ -4478,8 +4479,7 @@ ARMul_Emulate26 (ARMul_State * state)
isize) &
R15PCBITS));
#endif
- }
- else
+ } else if (instr != 0xDEADC0DE) // thumbemu uses 0xDEADCODE for debugging to catch non updates
ARMul_MCR (state, instr,
DEST);
}
@@ -4490,7 +4490,6 @@ ARMul_Emulate26 (ARMul_State * state)
/* Co-Processor Register Transfers (MRC) and Data Ops. */
- case 0xe0:
case 0xe1:
case 0xe3:
case 0xe5:
@@ -4534,23 +4533,7 @@ ARMul_Emulate26 (ARMul_State * state)
case 0xfd:
case 0xfe:
case 0xff:
- if (instr == ARMul_ABORTWORD
- && state->AbortAddr == pc) {
- /* A prefetch abort. */
- XScale_set_fsr_far (state,
- ARMul_CP15_R5_MMU_EXCPT,
- pc);
- ARMul_Abort (state,
- ARMul_PrefetchAbortV);
- break;
- }
- //sky_pref_t* pref = get_skyeye_pref();
- //if(pref->user_mode_sim){
- // ARMul_OSHandleSWI (state, BITS (0, 23));
- // break;
- //}
- HLE::CallSyscall(instr);
- ARMul_Abort (state, ARMul_SWIV);
+ HLE::CallSVC(instr);
break;
}
}
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 2c771cdda..e05667bea 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -17,8 +17,11 @@
#include "common/platform.h"
+
#if EMU_PLATFORM == PLATFORM_LINUX
#include <unistd.h>
+#elif EMU_PLATFORM == PLATFORM_WINDOWS
+#include <windows.h>
#endif
#include <math.h>
diff --git a/src/core/arm/interpreter/vfp/vfp.h b/src/core/arm/interpreter/vfp/vfp.h
index f738a615b..bbf4caeb0 100644
--- a/src/core/arm/interpreter/vfp/vfp.h
+++ b/src/core/arm/interpreter/vfp/vfp.h
@@ -21,7 +21,7 @@
#ifndef __VFP_H__
#define __VFP_H__
-#define DBG(...) DEBUG_LOG(ARM11, __VA_ARGS__)
+#define DBG(...) //DEBUG_LOG(ARM11, __VA_ARGS__)
#define vfpdebug //printf
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-28 20:50:29 +0000