2 files changed, 14 insertions, 11 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index a838fd25a..c779e3fd4 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -9,6 +9,8 @@
 #include "core/arm/dyncom/arm_dyncom.h"
 #include "core/arm/dyncom/arm_dyncom_interpreter.h"
 
+#include "core/core_timing.h"
+
 const static cpu_config_t s_arm11_cpu_info = {
     "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
 };
@@ -77,6 +79,9 @@ u64 ARM_DynCom::GetTicks() const {
 
 void ARM_DynCom::AddTicks(u64 ticks) {
     this->ticks += ticks;
+    down_count -= ticks;
+    if (down_count < 0)
+        CoreTiming::Advance();
 }
 
 void ARM_DynCom::ExecuteInstructions(int num_instructions) {
@@ -85,7 +90,8 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
     // Dyncom only breaks on instruction dispatch. This only happens on every instruction when
     // executing one instruction at a time. Otherwise, if a block is being executed, more
     // instructions may actually be executed than specified.
-    ticks += InterpreterMainLoop(state.get());
+    unsigned ticks_executed = InterpreterMainLoop(state.get());
+    AddTicks(ticks_executed);
 }
 
 void ARM_DynCom::SaveContext(ThreadContext& ctx) {
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 426fc6474..7c710ccde 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -5891,16 +5891,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
 
     SMULW_INST:
     {
-        if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
-            smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
-            int64_t rm = RM;
-            int64_t rn = RN;
-            if (inst_cream->m)
-                rm = BITS(rm, 16, 31);
-            else
-                rm = BITS(rm, 0, 15);
-            int64_t rst = rm * rn;
-            RD = BITS(rst, 16, 47);
+        if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+            smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
+
+            s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF);
+
+            s64 result = (s64)rm * (s64)(s32)RN;
+            RD = BITS(result, 16, 47);
         }
         cpu->Reg[15] += GET_INST_SIZE(cpu);
         INC_PC(sizeof(smlad_inst));