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-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp59
2 files changed, 39 insertions, 22 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index ffa627352..9f3b90fd0 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -42,7 +42,7 @@ const ISEITEM arm_instruction[] = {
{ "srs", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005 },
{ "rfe", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a },
- { "bkpt", 2, 3, 20, 31, 0x00000e12, 4, 7, 0x00000007 },
+ { "bkpt", 2, 3, 20, 27, 0x00000012, 4, 7, 0x00000007 },
{ "blx", 1, 3, 25, 31, 0x0000007d },
{ "cps", 3, 6, 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000 },
{ "pld", 4, 4, 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f },
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index a8b3c1276..c3dba8882 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -9,6 +9,7 @@
#include <unordered_map>
#include "common/logging/log.h"
+#include "common/profiler.h"
#include "core/mem_map.h"
#include "core/hle/hle.h"
@@ -20,6 +21,9 @@
#include "core/arm/skyeye_common/armmmu.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
+Common::Profiling::TimingCategory profile_execute("DynCom::Execute");
+Common::Profiling::TimingCategory profile_decode("DynCom::Decode");
+
enum {
COND = (1 << 0),
NON_BRANCH = (1 << 1),
@@ -792,6 +796,7 @@ typedef struct _stm_inst {
} stm_inst;
struct bkpt_inst {
+ u32 imm;
};
struct blx1_inst {
@@ -1371,7 +1376,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index)
inst_base->br = INDIRECT_BRANCH;
return inst_base;
}
-static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("BKPT"); }
+
+static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bkpt_inst));
+ bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->imm = BITS(inst, 8, 19) | BITS(inst, 0, 3);
+
+ return inst_base;
+}
+
static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index)
{
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst));
@@ -3553,6 +3573,8 @@ typedef struct instruction_set_encoding_item ISEITEM;
extern const ISEITEM arm_instruction[];
static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, addr_t addr) {
+ Common::Profiling::ScopeTimer timer_decode(profile_decode);
+
// Decode instruction, get index
// Allocate memory and init InsCream
// Go on next, until terminal instruction
@@ -3625,6 +3647,8 @@ static bool InAPrivilegedMode(ARMul_State* core) {
}
unsigned InterpreterMainLoop(ARMul_State* state) {
+ Common::Profiling::ScopeTimer timer_execute(profile_execute);
+
#undef RM
#undef RS
@@ -4081,6 +4105,16 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
GOTO_NEXT_INST;
}
BKPT_INST:
+ {
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
+ LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
+ }
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(bkpt_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
BLX_INST:
{
blx_inst *inst_cream = (blx_inst *)inst_base->component;
@@ -4396,12 +4430,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
unsigned int value = Memory::Read32(addr);
- if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- else {
- value = ROTATE_RIGHT_32(value,(8*(addr&0x3)));
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- }
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
if (BITS(inst_cream->inst, 12, 15) == 15) {
// For armv5t, should enter thumb when bits[0] is non-zero.
@@ -4424,12 +4453,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
unsigned int value = Memory::Read32(addr);
- if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- else {
- value = ROTATE_RIGHT_32(value,(8*(addr&0x3)));
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- }
+ cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
if (BITS(inst_cream->inst, 12, 15) == 15) {
// For armv5t, should enter thumb when bits[0] is non-zero.
@@ -4673,11 +4697,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
unsigned int value = Memory::Read32(addr);
cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
- else
- cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ROTATE_RIGHT_32(value,(8*(addr&0x3))) ;
-
if (BITS(inst_cream->inst, 12, 15) == 15) {
INC_PC(sizeof(ldst_inst));
goto DISPATCH;
@@ -4698,9 +4717,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
DEBUG_MSG;
} else {
if (inst_cream->cp_num == 15) {
- if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
- CP15_REG(CP15_MAIN_ID) = RD;
- } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
+ if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
CP15_REG(CP15_CONTROL) = RD;
} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-10 19:42:20 +0000