diff options
Diffstat (limited to 'src/core/arm/dyncom')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom.cpp | 46 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom.h | 59 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.cpp | 3 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.h | 45 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 1847 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.h | 2 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_run.cpp | 19 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_run.h | 15 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_thumb.cpp | 32 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_thumb.h | 6 |
10 files changed, 979 insertions, 1095 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index 9c4cc90f2..bbcbbdd2b 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp @@ -2,12 +2,12 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. -#include "core/arm/skyeye_common/armcpu.h" #include "core/arm/skyeye_common/armemu.h" #include "core/arm/skyeye_common/vfp/vfp.h" #include "core/arm/dyncom/arm_dyncom.h" #include "core/arm/dyncom/arm_dyncom_interpreter.h" +#include "core/arm/dyncom/arm_dyncom_run.h" #include "core/core.h" #include "core/core_timing.h" @@ -16,42 +16,36 @@ const static cpu_config_t s_arm11_cpu_info = { "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE }; -ARM_DynCom::ARM_DynCom() { +ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) { state = std::unique_ptr<ARMul_State>(new ARMul_State); - ARMul_EmulateInit(); - memset(state.get(), 0, sizeof(ARMul_State)); - - ARMul_NewState((ARMul_State*)state.get()); + ARMul_NewState(state.get()); + ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); - state->abort_model = 0; + state->abort_model = ABORT_BASE_RESTORED; state->cpu = (cpu_config_t*)&s_arm11_cpu_info; - state->bigendSig = LOW; - ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); + state->bigendSig = LOW; state->lateabtSig = LOW; + state->NirqSig = HIGH; // Reset the core to initial state - ARMul_CoProInit(state.get()); ARMul_Reset(state.get()); state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext - state->Emulate = 3; + state->Emulate = RUN; - state->pc = state->Reg[15] = 0x00000000; - state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack - state->servaddr = 0xFFFF0000; - state->NirqSig = HIGH; - - VFPInit(state.get()); // Initialize the VFP + // Switch to the desired privilege mode. + switch_mode(state.get(), initial_mode); - ARMul_EmulateInit(); + state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack + state->Reg[15] = 0x00000000; } ARM_DynCom::~ARM_DynCom() { } void ARM_DynCom::SetPC(u32 pc) { - state->pc = state->Reg[15] = pc; + state->Reg[15] = pc; } u32 ARM_DynCom::GetPC() const { @@ -95,6 +89,16 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) { AddTicks(ticks_executed); } +void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) { + memset(&context, 0, sizeof(Core::ThreadContext)); + + context.cpu_registers[0] = arg; + context.pc = entry_point; + context.sp = stack_top; + context.cpsr = 0x1F; // Usermode + context.mode = 8; // Instructs dyncom CPU core to start execution as if it's "resuming" a thread. +} + void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); @@ -107,7 +111,6 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { ctx.fpscr = state->VFP[1]; ctx.fpexc = state->VFP[2]; - ctx.reg_15 = state->Reg[15]; ctx.mode = state->NextInstr; } @@ -117,13 +120,12 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) { state->Reg[13] = ctx.sp; state->Reg[14] = ctx.lr; - state->pc = ctx.pc; + state->Reg[15] = ctx.pc; state->Cpsr = ctx.cpsr; state->VFP[1] = ctx.fpscr; state->VFP[2] = ctx.fpexc; - state->Reg[15] = ctx.reg_15; state->NextInstr = ctx.mode; } diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h index f16fb070c..213cac1ad 100644 --- a/src/core/arm/dyncom/arm_dyncom.h +++ b/src/core/arm/dyncom/arm_dyncom.h @@ -13,79 +13,24 @@ class ARM_DynCom final : virtual public ARM_Interface { public: - - ARM_DynCom(); + ARM_DynCom(PrivilegeMode initial_mode); ~ARM_DynCom(); - /** - * Set the Program Counter to an address - * @param pc Address to set PC to - */ void SetPC(u32 pc) override; - - /* - * Get the current Program Counter - * @return Returns current PC - */ u32 GetPC() const override; - - /** - * Get an ARM register - * @param index Register index (0-15) - * @return Returns the value in the register - */ u32 GetReg(int index) const override; - - /** - * Set an ARM register - * @param index Register index (0-15) - * @param value Value to set register to - */ void SetReg(int index, u32 value) override; - - /** - * Get the current CPSR register - * @return Returns the value of the CPSR register - */ u32 GetCPSR() const override; - - /** - * Set the current CPSR register - * @param cpsr Value to set CPSR to - */ void SetCPSR(u32 cpsr) override; - /** - * Returns the number of clock ticks since the last reset - * @return Returns number of clock ticks - */ u64 GetTicks() const override; - - /** - * Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time) - * @param ticks Number of ticks to advance the CPU core - */ void AddTicks(u64 ticks) override; - /** - * Saves the current CPU context - * @param ctx Thread context to save - */ + void ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg); void SaveContext(Core::ThreadContext& ctx) override; - - /** - * Loads a CPU context - * @param ctx Thread context to load - */ void LoadContext(const Core::ThreadContext& ctx) override; - /// Prepare core for thread reschedule (if needed to correctly handle state) void PrepareReschedule() override; - - /** - * Executes the given number of instructions - * @param num_instructions Number of instructions to executes - */ void ExecuteInstructions(int num_instructions) override; private: diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 0927eece1..9f3b90fd0 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -2,7 +2,6 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. -#include "core/arm/skyeye_common/arm_regformat.h" #include "core/arm/skyeye_common/armdefs.h" #include "core/arm/dyncom/arm_dyncom_dec.h" @@ -43,7 +42,7 @@ const ISEITEM arm_instruction[] = { { "srs", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005 }, { "rfe", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a }, - { "bkpt", 2, 3, 20, 31, 0x00000e12, 4, 7, 0x00000007 }, + { "bkpt", 2, 3, 20, 27, 0x00000012, 4, 7, 0x00000007 }, { "blx", 1, 3, 25, 31, 0x0000007d }, { "cps", 3, 6, 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000 }, { "pld", 4, 4, 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f }, diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h index 58784aeea..ee8ff5992 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.h +++ b/src/core/arm/dyncom/arm_dyncom_dec.h @@ -6,14 +6,6 @@ #define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) #define BIT(n) ((instr >> (n)) & 1) -#define BAD do { printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); } while(0); -#define ptr_N cpu->ptr_N -#define ptr_Z cpu->ptr_Z -#define ptr_C cpu->ptr_C -#define ptr_V cpu->ptr_V -#define ptr_I cpu->ptr_I -#define ptr_T cpu->ptr_T -#define ptr_CPSR cpu->ptr_gpr[16] // For MUL instructions #define RDHi ((instr >> 16) & 0xF) @@ -49,24 +41,6 @@ #define SBIT BIT(20) #define DESTReg (BITS (12, 15)) -// They are in unused state, give a corrent value when using -#define IS_V5E 0 -#define IS_V5 0 -#define IS_V6 0 -#define LHSReg 0 - -// Temp define the using the pc reg need implement a flow -#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2)) - -#define OPERAND operand(cpu,instr,bb,NULL) -#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco) -#define BOPERAND boperand(instr) - -#define CHECK_RN_PC (RN == 15 ? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)) : R(RN)) -#define CHECK_RN_PC_WA (RN == 15 ? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)) : R(RN)) - -#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE)))) - int decode_arm_instr(uint32_t instr, int32_t *idx); enum DECODE_STATUS { @@ -83,23 +57,8 @@ struct instruction_set_encoding_item { typedef struct instruction_set_encoding_item ISEITEM; -#define RECORD_WB(value, flag) { cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag; } -#define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag) - -#define EXECUTE_WB(base_reg) { if(cpu->dyncom_engine->wb_flag) LET(base_reg, cpu->dyncom_engine->wb_value); } - -inline int get_reg_count(uint32_t instr) { - int i = BITS(0, 15); - int count = 0; - while (i) { - if (i & 1) - count++; - i = i >> 1; - } - return count; -} - -enum ARMVER { +// ARM versions +enum { INVALID = 0, ARMALL, ARMV4, diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index bf864c7a7..3b508f617 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5,63 +5,43 @@ #define CITRA_IGNORE_EXIT(x) #include <algorithm> -#include <unordered_map> -#include <stdio.h> -#include <assert.h> #include <cstdio> -#include <vector> +#include <unordered_map> -using namespace std; +#include "common/logging/log.h" +#include "core/mem_map.h" +#include "core/hle/hle.h" +#include "core/arm/disassembler/arm_disasm.h" +#include "core/arm/dyncom/arm_dyncom_interpreter.h" +#include "core/arm/dyncom/arm_dyncom_thumb.h" +#include "core/arm/dyncom/arm_dyncom_run.h" #include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armmmu.h" -#include "arm_dyncom_thumb.h" -#include "arm_dyncom_run.h" #include "core/arm/skyeye_common/vfp/vfp.h" -#include "core/arm/disassembler/arm_disasm.h" - -#include "core/mem_map.h" -#include "core/hle/hle.h" enum { - COND = (1 << 0), - NON_BRANCH = (1 << 1), - DIRECT_BRANCH = (1 << 2), + COND = (1 << 0), + NON_BRANCH = (1 << 1), + DIRECT_BRANCH = (1 << 2), INDIRECT_BRANCH = (1 << 3), - CALL = (1 << 4), - RET = (1 << 5), - END_OF_PAGE = (1 << 6), - THUMB = (1 << 7) + CALL = (1 << 4), + RET = (1 << 5), + END_OF_PAGE = (1 << 6), + THUMB = (1 << 7) }; -#define USER_MODE_OPT 1 -#define HYBRID_MODE 0 // Enable for JIT mode - -#define THRESHOLD 1000 -#define DURATION 500 - -#define CHECK_RS if(RS == 15) rs += 8 -#define CHECK_RM if(RM == 15) rm += 8 - -#undef BITS -#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) -#define BIT(s, n) ((s >> (n)) & 1) #define RM BITS(sht_oper, 0, 3) #define RS BITS(sht_oper, 8, 11) -#define glue(x, y) x ## y -#define DPO(s) glue(DataProcessingOperands, s) -#define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i)) -#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i)) -#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32) -#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32) - -#define rotr(x,n) ( (x >> n) | ((x & ((1 << (n + 1)) - 1)) << (32 - n)) ) +#define glue(x, y) x ## y +#define DPO(s) glue(DataProcessingOperands, s) +#define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i)) +#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i)) +#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32) +#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32) -extern void switch_mode(arm_core_t *core, uint32_t mode); - -typedef arm_core_t arm_processor; -typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper); +typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper); // Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag. // This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to @@ -69,7 +49,7 @@ typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper); static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8; // Exclusive memory access -static int exclusive_detect(ARMul_State* state, ARMword addr){ +static int exclusive_detect(ARMul_State* state, ARMword addr) { if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK)) return 0; else @@ -85,7 +65,7 @@ static void remove_exclusive(ARMul_State* state, ARMword addr){ state->exclusive_tag = 0xFFFFFFFF; } -unsigned int DPO(Immediate)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int immed_8 = BITS(sht_oper, 0, 7); unsigned int rotate_imm = BITS(sht_oper, 8, 11); unsigned int shifter_operand = ROTATE_RIGHT_32(immed_8, rotate_imm * 2); @@ -96,14 +76,14 @@ unsigned int DPO(Immediate)(arm_processor *cpu, unsigned int sht_oper) { return shifter_operand; } -unsigned int DPO(Register)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(Register)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int shifter_operand = rm; cpu->shifter_carry_out = cpu->CFlag; return shifter_operand; } -unsigned int DPO(LogicalShiftLeftByImmediate)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(LogicalShiftLeftByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { int shift_imm = BITS(sht_oper, 7, 11); unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int shifter_operand; @@ -117,7 +97,7 @@ unsigned int DPO(LogicalShiftLeftByImmediate)(arm_processor *cpu, unsigned int s return shifter_operand; } -unsigned int DPO(LogicalShiftLeftByRegister)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(LogicalShiftLeftByRegister)(ARMul_State* cpu, unsigned int sht_oper) { int shifter_operand; unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int rs = CHECK_READ_REG15(cpu, RS); @@ -137,7 +117,7 @@ unsigned int DPO(LogicalShiftLeftByRegister)(arm_processor *cpu, unsigned int sh return shifter_operand; } -unsigned int DPO(LogicalShiftRightByImmediate)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(LogicalShiftRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int shifter_operand; int shift_imm = BITS(sht_oper, 7, 11); @@ -151,7 +131,7 @@ unsigned int DPO(LogicalShiftRightByImmediate)(arm_processor *cpu, unsigned int return shifter_operand; } -unsigned int DPO(LogicalShiftRightByRegister)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(LogicalShiftRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int rs = CHECK_READ_REG15(cpu, RS); unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int shifter_operand; @@ -171,18 +151,16 @@ unsigned int DPO(LogicalShiftRightByRegister)(arm_processor *cpu, unsigned int s return shifter_operand; } -unsigned int DPO(ArithmeticShiftRightByImmediate)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(ArithmeticShiftRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int shifter_operand; int shift_imm = BITS(sht_oper, 7, 11); if (shift_imm == 0) { - if (BIT(rm, 31)) { + if (BIT(rm, 31) == 0) shifter_operand = 0; - cpu->shifter_carry_out = BIT(rm, 31); - } else { + else shifter_operand = 0xFFFFFFFF; - cpu->shifter_carry_out = BIT(rm, 31); - } + cpu->shifter_carry_out = BIT(rm, 31); } else { shifter_operand = static_cast<int>(rm) >> shift_imm; cpu->shifter_carry_out = BIT(rm, shift_imm - 1); @@ -190,7 +168,7 @@ unsigned int DPO(ArithmeticShiftRightByImmediate)(arm_processor *cpu, unsigned i return shifter_operand; } -unsigned int DPO(ArithmeticShiftRightByRegister)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(ArithmeticShiftRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int rs = CHECK_READ_REG15(cpu, RS); unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int shifter_operand; @@ -210,7 +188,7 @@ unsigned int DPO(ArithmeticShiftRightByRegister)(arm_processor *cpu, unsigned in return shifter_operand; } -unsigned int DPO(RotateRightByImmediate)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(RotateRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int shifter_operand; unsigned int rm = CHECK_READ_REG15(cpu, RM); int shift_imm = BITS(sht_oper, 7, 11); @@ -224,7 +202,7 @@ unsigned int DPO(RotateRightByImmediate)(arm_processor *cpu, unsigned int sht_op return shifter_operand; } -unsigned int DPO(RotateRightByRegister)(arm_processor *cpu, unsigned int sht_oper) { +static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) { unsigned int rm = CHECK_READ_REG15(cpu, RM); unsigned int rs = CHECK_READ_REG15(cpu, RS); unsigned int shifter_operand; @@ -241,46 +219,7 @@ unsigned int DPO(RotateRightByRegister)(arm_processor *cpu, unsigned int sht_ope return shifter_operand; } -typedef struct _MiscImmeData { - unsigned int U; - unsigned int Rn; - unsigned int offset_8; -} MiscLSData; - -typedef struct _MiscRegData { - unsigned int U; - unsigned int Rn; - unsigned int Rm; -} MiscRegData; - -typedef struct _MiscImmePreIdx { - unsigned int offset_8; - unsigned int U; - unsigned int Rn; -} MiscImmePreIdx; - -typedef struct _MiscRegPreIdx { - unsigned int U; - unsigned int Rn; - unsigned int Rm; -} MiscRegPreIdx; - -typedef struct _MiscImmePstIdx { - unsigned int offset_8; - unsigned int U; - unsigned int Rn; -} MIscImmePstIdx; - -typedef struct _MiscRegPstIdx { - unsigned int Rn; - unsigned int Rm; - unsigned int U; -} MiscRegPstIdx; - -typedef struct _LSWordorUnsignedByte { -} LDnST; - -typedef void (*get_addr_fp_t)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw); +typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw); typedef struct _ldst_inst { unsigned int inst; @@ -288,9 +227,10 @@ typedef struct _ldst_inst { } ldst_inst; #define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0) -int CondPassed(arm_processor *cpu, unsigned int cond); -#define LnSWoUB(s) glue(LnSWoUB, s) -#define MLnS(s) glue(MLnS, s) +int CondPassed(ARMul_State* cpu, unsigned int cond); + +#define LnSWoUB(s) glue(LnSWoUB, s) +#define MLnS(s) glue(MLnS, s) #define LdnStM(s) glue(LdnStM, s) #define W_BIT BIT(inst, 21) @@ -299,7 +239,7 @@ int CondPassed(arm_processor *cpu, unsigned int cond); #define P_BIT BIT(inst, 24) #define OFFSET_12 BITS(inst, 0, 11) -void LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int addr; @@ -311,7 +251,7 @@ void LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned in virt_addr = addr; } -void LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); @@ -326,7 +266,7 @@ void LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int virt_addr = addr; } -void LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); @@ -338,7 +278,7 @@ void LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsign virt_addr = addr; } -void LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int addr; @@ -353,7 +293,7 @@ void LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigne cpu->Reg[Rn] = addr; } -void MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int addr; unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); @@ -371,7 +311,7 @@ void MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned in cpu->Reg[Rn] = addr; } -void LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); @@ -390,7 +330,7 @@ void LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned } } -void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int shift = BITS(inst, 5, 6); unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -412,10 +352,21 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un } break; case 2: - DEBUG_MSG; + if (shift_imm == 0) { // ASR #32 + if (BIT(rm, 31) == 1) + index = 0xFFFFFFFF; + else + index = 0; + } else { + index = static_cast<int>(rm) >> shift_imm; + } break; case 3: - DEBUG_MSG; + if (shift_imm == 0) { + index = (cpu->CFlag << 31) | (rm >> 1); + } else { + index = ROTATE_RIGHT_32(rm, shift_imm); + } break; } @@ -430,7 +381,7 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un cpu->Reg[Rn] = addr; } -void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int shift = BITS(inst, 5, 6); unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -451,10 +402,21 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u } break; case 2: - DEBUG_MSG; + if (shift_imm == 0) { // ASR #32 + if (BIT(rm, 31) == 1) + index = 0xFFFFFFFF; + else + index = 0; + } else { + index = static_cast<int>(rm) >> shift_imm; + } break; case 3: - DEBUG_MSG; + if (shift_imm == 0) { + index = (cpu->CFlag << 31) | (rm >> 1); + } else { + index = ROTATE_RIGHT_32(rm, shift_imm); + } break; } @@ -468,7 +430,7 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u } } -void LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); @@ -484,7 +446,7 @@ void LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigne } } -void MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int immedL = BITS(inst, 0, 3); unsigned int immedH = BITS(inst, 8, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -500,7 +462,7 @@ void MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int & virt_addr = addr; } -void MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int addr; unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); @@ -515,7 +477,7 @@ void MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &v virt_addr = addr; } -void MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int immedH = BITS(inst, 8, 11); unsigned int immedL = BITS(inst, 0, 3); @@ -534,7 +496,7 @@ void MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned i cpu->Reg[Rn] = addr; } -void MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int immedH = BITS(inst, 8, 11); unsigned int immedL = BITS(inst, 0, 3); @@ -553,7 +515,7 @@ void MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned } } -void MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); @@ -568,7 +530,7 @@ void MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned i } } -void LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int i = BITS(inst, 0, 15); int count = 0; @@ -584,7 +546,7 @@ void LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int cpu->Reg[Rn] -= count * 4; } -void LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int i = BITS(inst, 0, 15); int count = 0; @@ -600,7 +562,7 @@ void LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int cpu->Reg[Rn] += count * 4; } -void LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int i = BITS(inst, 0, 15); int count = 0; @@ -616,7 +578,7 @@ void LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int cpu->Reg[Rn] += count * 4; } -void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int Rn = BITS(inst, 16, 19); unsigned int i = BITS(inst, 0, 15); int count = 0; @@ -634,7 +596,7 @@ void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int } } -void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) { +static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) { unsigned int shift = BITS(inst, 5, 6); unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); @@ -656,8 +618,8 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign } break; case 2: - if (shift_imm == 0){ // ASR #32 - if (rm >> 31) + if (shift_imm == 0) { // ASR #32 + if (BIT(rm, 31) == 1) index = 0xFFFFFFFF; else index = 0; @@ -666,7 +628,11 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign } break; case 3: - DEBUG_MSG; + if (shift_imm == 0) { + index = (cpu->CFlag << 31) | (rm >> 1); + } else { + index = ROTATE_RIGHT_32(rm, shift_imm); + } break; } @@ -678,9 +644,6 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign virt_addr = addr; } -#define ISNEG(n) (n < 0) -#define ISPOS(n) (n >= 0) - typedef struct _arm_inst { unsigned int idx; unsigned int cond; @@ -829,6 +792,7 @@ typedef struct _stm_inst { } stm_inst; struct bkpt_inst { + u32 imm; }; struct blx1_inst { @@ -1148,7 +1112,7 @@ inline void *AllocBuffer(unsigned int size) { return (void *)&inst_buf[start]; } -int CondPassed(arm_processor *cpu, unsigned int cond) { +int CondPassed(ARMul_State* cpu, unsigned int cond) { #define NFLAG cpu->NFlag #define ZFLAG cpu->ZFlag #define CFLAG cpu->CFlag @@ -1216,7 +1180,7 @@ enum DECODE_STATUS { int decode_arm_instr(uint32_t instr, int32_t *idx); -shtop_fp_t get_shtop(unsigned int inst) { +static shtop_fp_t get_shtop(unsigned int inst) { if (BIT(inst, 25)) { return DPO(Immediate); } else if (BITS(inst, 4, 11) == 0) { @@ -1241,7 +1205,7 @@ shtop_fp_t get_shtop(unsigned int inst) { return nullptr; } -get_addr_fp_t get_calc_addr_op(unsigned int inst) { +static get_addr_fp_t get_calc_addr_op(unsigned int inst) { if (BITS(inst, 24, 27) == 5 && BIT(inst, 21) == 0) { return LnSWoUB(ImmediateOffset); } else if (BITS(inst, 24, 27) == 7 && BIT(inst, 21) == 0 && BITS(inst, 4, 11) == 0) { @@ -1295,20 +1259,20 @@ get_addr_fp_t get_calc_addr_op(unsigned int inst) { CITRA_IGNORE_EXIT(-1); \ return nullptr; -ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst)); adc_inst *inst_cream = (adc_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1318,20 +1282,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(add_inst)); add_inst *inst_cream = (add_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1341,20 +1305,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(and_inst)); and_inst *inst_cream = (and_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1363,7 +1327,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) inst_base->br = INDIRECT_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) { #define POSBRANCH ((inst & 0x7fffff) << 2) #define NEGBRANCH ((0xff000000 |(inst & 0xffffff)) << 2) @@ -1371,9 +1335,9 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bbl_inst)); bbl_inst *inst_cream = (bbl_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = DIRECT_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; if (BIT(inst, 24)) inst_base->br = CALL; @@ -1385,20 +1349,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bic_inst)); bic_inst *inst_cream = (bic_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1408,15 +1372,30 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) inst_base->br = INDIRECT_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("BKPT"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) + +static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bkpt_inst)); + bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->imm = BITS(inst, 8, 19) | BITS(inst, 0, 3); + + return inst_base; +} + +static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst)); blx_inst *inst_cream = (blx_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = INDIRECT_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = INDIRECT_BRANCH; inst_cream->inst = inst; if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { @@ -1427,7 +1406,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bx_inst)); bx_inst *inst_cream = (bx_inst *)inst_base->component; @@ -1440,125 +1419,125 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(bx)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index){ +static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst)); cdp_inst *inst_cream = (cdp_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->CRm = BITS(inst, 0, 3); - inst_cream->CRd = BITS(inst, 12, 15); - inst_cream->CRn = BITS(inst, 16, 19); + inst_cream->CRm = BITS(inst, 0, 3); + inst_cream->CRd = BITS(inst, 12, 15); + inst_cream->CRn = BITS(inst, 16, 19); inst_cream->cp_num = BITS(inst, 8, 11); - inst_cream->opcode_2 = BITS(inst, 5, 7); - inst_cream->opcode_1 = BITS(inst, 20, 23); + inst_cream->opcode_2 = BITS(inst, 5, 7); + inst_cream->opcode_1 = BITS(inst, 20, 23); inst_cream->inst = inst; LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clrex_inst)); - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clz_inst)); clz_inst *inst_cream = (clz_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rd = BITS(inst, 12, 15); if (CHECK_RM) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmn_inst)); cmn_inst *inst_cream = (cmn_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - //inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - //inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->Rn = BITS(inst, 16, 19); + if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmp_inst)); cmp_inst *inst_cream = (cmp_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->I = BIT(inst, 25); + inst_cream->Rn = BITS(inst, 16, 19); if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cps_inst)); cps_inst *inst_cream = (cps_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->imod0 = BIT(inst, 18); inst_cream->imod1 = BIT(inst, 19); inst_cream->mmod = BIT(inst, 17); - inst_cream->A = BIT(inst, 8); - inst_cream->I = BIT(inst, 7); - inst_cream->F = BIT(inst, 6); + inst_cream->A = BIT(inst, 8); + inst_cream->I = BIT(inst, 7); + inst_cream->F = BIT(inst, 6); inst_cream->mode = BITS(inst, 0, 4); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); mov_inst *inst_cream = (mov_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); @@ -1567,20 +1546,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(eor_inst)); eor_inst *inst_cream = (eor_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); if (CHECK_RN) inst_base->load_r15 = 1; inst_cream->shifter_operand = BITS(inst, 0, 11); @@ -1590,23 +1569,23 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldc_inst)); - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -1616,14 +1595,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rd = BITS(inst, 12, 15); @@ -1634,14 +1613,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->inst = inst; @@ -1653,14 +1632,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->inst = inst; @@ -1672,14 +1651,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); uxth_inst *inst_cream = (uxth_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rd = BITS(inst, 12, 15); @@ -1690,14 +1669,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtah_inst)); uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rn = BITS(inst, 16, 19); @@ -1709,14 +1688,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -1726,48 +1705,44 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; - if (I_BIT == 0) { + if (BITS(inst, 25, 27) == 2) { inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); } else { DEBUG_MSG; } - #if 0 - inst_cream->get_addr = get_calc_addr_op(inst); - if(inst == 0x54f13001) { - DEBUG_LOG(ARM11, "get_calc_addr_op:%llx\n", inst_cream->get_addr); - } - #endif if (BITS(inst, 12, 15) == 15) { inst_base->br = INDIRECT_BRANCH; } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; @@ -1781,26 +1756,26 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ldrex)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ldrex)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ldrex)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -1810,14 +1785,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -1827,14 +1802,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -1844,19 +1819,26 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; - if (I_BIT == 0) { + if (BITS(inst, 25, 27) == 2) { inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); } else { + // Reaching this would indicate the thumb version + // of this instruction, however the 3DS CPU doesn't + // support this variant (the 3DS CPU is only ARMv6K, + // while this variant is added in ARMv6T2). + // So it's sufficient for citra to not implement this. DEBUG_MSG; } @@ -1865,13 +1847,13 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mcr_inst)); mcr_inst *inst_cream = (mcr_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->crn = BITS(inst, 16, 19); inst_cream->crm = BITS(inst, 0, 3); @@ -1882,40 +1864,40 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) inst_cream->inst = inst; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MCRR"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MCRR"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst)); mla_inst *inst_cream = (mla_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 12, 15); - inst_cream->Rd = BITS(inst, 16, 19); - inst_cream->Rs = BITS(inst, 8, 11); - inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 12, 15); + inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rm = BITS(inst, 0, 3); if (CHECK_RM || CHECK_RN || CHECK_RS) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); mov_inst *inst_cream = (mov_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); @@ -1924,13 +1906,13 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrc_inst)); mrc_inst *inst_cream = (mrc_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->crn = BITS(inst, 16, 19); inst_cream->crm = BITS(inst, 0, 3); @@ -1941,29 +1923,29 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) inst_cream->inst = inst; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MRRC"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MRRC"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst)); mrs_inst *inst_cream = (mrs_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->R = BIT(inst, 22); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->R = BIT(inst, 22); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(msr_inst)); msr_inst *inst_cream = (msr_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->field_mask = BITS(inst, 16, 19); inst_cream->R = BIT(inst, 22); @@ -1971,37 +1953,37 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mul_inst)); mul_inst *inst_cream = (mul_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); - inst_cream->Rd = BITS(inst, 16, 19); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->Rd = BITS(inst, 16, 19); if (CHECK_RM || CHECK_RS) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mvn_inst)); mvn_inst *inst_cream = (mvn_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); @@ -2011,20 +1993,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(orr_inst)); orr_inst *inst_cream = (orr_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rd = BITS(inst, 12, 15); - inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->Rn = BITS(inst, 16, 19); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); @@ -2036,7 +2018,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst)); pkh_inst *inst_cream = (pkh_inst *)inst_base->component; @@ -2054,24 +2036,24 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(pkhbt)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst)); - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -2088,20 +2070,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -2119,28 +2101,28 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(qadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst)); rev_inst* const inst_cream = (rev_inst*)inst_base->component; @@ -2157,30 +2139,30 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(rev)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(rev)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("RFE"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("RFE"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst)); rsb_inst *inst_cream = (rsb_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); if (CHECK_RN) @@ -2191,20 +2173,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsc_inst)); rsc_inst *inst_cream = (rsc_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); if (CHECK_RN) @@ -2215,7 +2197,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -2233,41 +2215,41 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst)); sbc_inst *inst_cream = (sbc_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); if (CHECK_RN) @@ -2278,7 +2260,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -2297,9 +2279,9 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -2317,48 +2299,48 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(shadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst)); smla_inst *inst_cream = (smla_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->x = BIT(inst, 5); - inst_cream->y = BIT(inst, 6); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->x = BIT(inst, 5); + inst_cream->y = BIT(inst, 6); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->Rd = BITS(inst, 16, 19); inst_cream->Rn = BITS(inst, 12, 15); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; @@ -2378,32 +2360,32 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlad)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlad)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlad)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); umlal_inst *inst_cream = (umlal_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->RdLo = BITS(inst, 12, 15); @@ -2412,7 +2394,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst)); smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; @@ -2432,7 +2414,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; @@ -2451,7 +2433,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlald_inst)); smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; @@ -2471,12 +2453,12 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smlald)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; @@ -2496,23 +2478,23 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smmla)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(smmla)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst)); smul_inst *inst_cream = (smul_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rd = BITS(inst, 16, 19); @@ -2527,19 +2509,19 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); umull_inst *inst_cream = (umull_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->S = BIT(inst, 20); - inst_cream->Rm = BITS(inst, 0, 3); - inst_cream->Rs = BITS(inst, 8, 11); + inst_cream->S = BIT(inst, 20); + inst_cream->Rm = BITS(inst, 0, 3); + inst_cream->Rs = BITS(inst, 8, 11); inst_cream->RdHi = BITS(inst, 16, 19); inst_cream->RdLo = BITS(inst, 12, 15); @@ -2548,27 +2530,27 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); smlad_inst *inst_cream = (smlad_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->m = BIT(inst, 6); - inst_cream->Rm = BITS(inst, 8, 11); - inst_cream->Rn = BITS(inst, 0, 3); + inst_cream->m = BIT(inst, 6); + inst_cream->Rm = BITS(inst, 8, 11); + inst_cream->Rn = BITS(inst, 0, 3); inst_cream->Rd = BITS(inst, 16, 19); if (CHECK_RM || CHECK_RN) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); } -ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; @@ -2586,7 +2568,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; @@ -2603,36 +2585,36 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst)); - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rd = BITS(inst, 12, 15); @@ -2643,14 +2625,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -2660,14 +2642,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); uxth_inst *inst_cream = (uxth_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rd = BITS(inst, 12, 15); @@ -2678,14 +2660,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->Rd = BITS(inst, 12, 15); @@ -2695,14 +2677,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -2712,19 +2694,21 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; -// inst_cream->get_addr = get_calc_addr_op(inst); - if (I_BIT == 0) { + + if (BITS(inst, 25, 27) == 2) { inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); } else { DEBUG_MSG; } @@ -2734,13 +2718,13 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ +static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -2750,7 +2734,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component; @@ -2765,26 +2749,26 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(strex)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(strex)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(strex)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; inst_cream->get_addr = get_calc_addr_op(inst); @@ -2794,19 +2778,26 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) { - arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; + arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_cream->inst = inst; - if (I_BIT == 0) { + if (BITS(inst, 25, 27) == 2) { inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); + } else if (BITS(inst, 25, 27) == 3) { + inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); } else { + // Reaching this would indicate the thumb version + // of this instruction, however the 3DS CPU doesn't + // support this variant (the 3DS CPU is only ARMv6K, + // while this variant is added in ARMv6T2). + // So it's sufficient for citra to not implement this. DEBUG_MSG; } @@ -2815,20 +2806,20 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sub_inst)); sub_inst *inst_cream = (sub_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; - inst_cream->I = BIT(inst, 25); - inst_cream->S = BIT(inst, 20); - inst_cream->Rn = BITS(inst, 16, 19); - inst_cream->Rd = BITS(inst, 12, 15); + inst_cream->I = BIT(inst, 25); + inst_cream->S = BIT(inst, 20); + inst_cream->Rn = BITS(inst, 16, 19); + inst_cream->Rd = BITS(inst, 12, 15); inst_cream->shifter_operand = BITS(inst, 0, 11); inst_cream->shtop_func = get_shtop(inst); if (inst_cream->Rd == 15) { @@ -2839,7 +2830,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swi_inst)); swi_inst *inst_cream = (swi_inst *)inst_base->component; @@ -2851,7 +2842,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) inst_cream->num = BITS(inst, 0, 23); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); swp_inst *inst_cream = (swp_inst *)inst_base->component; @@ -2869,7 +2860,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ +static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); swp_inst *inst_cream = (swp_inst *)inst_base->component; @@ -2886,7 +2877,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ } return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component; @@ -2903,7 +2894,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; @@ -2920,13 +2911,12 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(sxtab16)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index){ - LOG_WARNING(Core_ARM11, "SXTAH untested"); +static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst)); sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component; @@ -2943,7 +2933,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index){ return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst)); teq_inst *inst_cream = (teq_inst *)inst_base->component; @@ -2962,7 +2952,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) inst_base->load_r15 = 1; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(tst_inst)); tst_inst *inst_cream = (tst_inst *)inst_base->component; @@ -2987,7 +2977,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -3005,28 +2995,28 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -3044,27 +3034,27 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uhadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umaal_inst)); umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; @@ -3084,14 +3074,14 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); umlal_inst *inst_cream = (umlal_inst *)inst_base->component; - inst_base->cond = BITS(inst, 28, 31); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->cond = BITS(inst, 28, 31); + inst_base->idx = index; + inst_base->br = NON_BRANCH; inst_base->load_r15 = 0; inst_cream->S = BIT(inst, 20); @@ -3105,7 +3095,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); umull_inst *inst_cream = (umull_inst *)inst_base->component; @@ -3126,55 +3116,55 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_2_thumb)); b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component; - inst_cream->imm = ((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0); + inst_cream->imm = ((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0); - inst_base->idx = index; - inst_base->br = DIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_cond_thumb)); b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component; - inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0)); - inst_cream->cond = ((tinst >> 8) & 0xf); - inst_base->idx = index; - inst_base->br = DIRECT_BRANCH; + inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0)); + inst_cream->cond = ((tinst >> 8) & 0xf); + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_1_thumb)); bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component; - inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0)); + inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0)); - inst_base->idx = index; - inst_base->br = NON_BRANCH; + inst_base->idx = index; + inst_base->br = NON_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_2_thumb)); bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component; - inst_cream->imm = (tinst & 0x07FF) << 1; + inst_cream->imm = (tinst & 0x07FF) << 1; - inst_base->idx = index; - inst_base->br = DIRECT_BRANCH; + inst_base->idx = index; + inst_base->br = DIRECT_BRANCH; return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_1_thumb)); blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component; @@ -3187,7 +3177,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -3205,27 +3195,27 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uqadd8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; @@ -3237,26 +3227,27 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) inst_cream->op1 = BITS(inst, 20, 24); inst_cream->op2 = BITS(inst, 5, 7); + inst_cream->Rd = BITS(inst, 16, 19); inst_cream->Rm = BITS(inst, 8, 11); inst_cream->Rn = BITS(inst, 0, 3); inst_cream->Ra = BITS(inst, 12, 15); return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(usada8)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ssat)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(ssat16)(inst, index); } -ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; @@ -3273,7 +3264,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) return inst_base; } -ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) +static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) { return INTERPRETER_TRANSLATE(uxtab16)(inst, index); } @@ -3491,14 +3482,13 @@ const transop_fp_t arm_instruction_trans[] = { }; typedef std::unordered_map<u32, int> bb_map; -bb_map CreamCache; +static bb_map CreamCache; -void insert_bb(unsigned int addr, int start) { +static void insert_bb(unsigned int addr, int start) { CreamCache[addr] = start; } -#define TRANS_THRESHOLD 65000 -int find_bb(unsigned int addr, int &start) { +static int find_bb(unsigned int addr, int& start) { int ret = -1; bb_map::const_iterator it = CreamCache.find(addr); if (it != CreamCache.end()) { @@ -3515,7 +3505,7 @@ enum { FETCH_FAILURE }; -static tdstate decode_thumb_instr(arm_processor *cpu, uint32_t inst, addr_t addr, uint32_t *arm_inst, uint32_t* inst_size, ARM_INST_PTR* ptr_inst_base){ +static tdstate decode_thumb_instr(ARMul_State* cpu, uint32_t inst, addr_t addr, uint32_t* arm_inst, uint32_t* inst_size, ARM_INST_PTR* ptr_inst_base){ // Check if in Thumb mode tdstate ret = thumb_translate (addr, inst, arm_inst, inst_size); if(ret == t_branch){ @@ -3533,7 +3523,6 @@ static tdstate decode_thumb_instr(arm_processor *cpu, uint32_t inst, addr_t addr case 26: case 27: if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){ - u32 cond = (tinstr & 0x0F00) >> 8; inst_index = table_length - 4; *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index); } else { @@ -3579,24 +3568,7 @@ typedef struct instruction_set_encoding_item ISEITEM; extern const ISEITEM arm_instruction[]; -vector<uint64_t> code_page_set; - -void flush_bb(uint32_t addr) { - bb_map::iterator it; - uint32_t start; - - addr &= 0xfffff000; - for (it = CreamCache.begin(); it != CreamCache.end(); ) { - start = static_cast<uint32_t>(it->first); - start &= 0xfffff000; - if (start == addr) { - CreamCache.erase(it++); - } else - ++it; - } -} - -int InterpreterTranslate(arm_processor *cpu, int &bb_start, addr_t addr) { +static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, addr_t addr) { // Decode instruction, get index // Allocate memory and init InsCream // Go on next, until terminal instruction @@ -3652,9 +3624,7 @@ translated: return KEEP_GOING; } -#define LOG_IN_CLR skyeye_printf_in_color - -int clz(unsigned int x) { +static int clz(unsigned int x) { int n; if (x == 0) return (32); n = 1; @@ -3666,13 +3636,14 @@ int clz(unsigned int x) { return n; } -unsigned arm_dyncom_SWI (ARMul_State * state, ARMword number); - -static bool InAPrivilegedMode(arm_core_t *core) { +static bool InAPrivilegedMode(ARMul_State* core) { return (core->Mode != USER32MODE); } unsigned InterpreterMainLoop(ARMul_State* state) { + #undef RM + #undef RS + #define CRn inst_cream->crn #define OPCODE_2 inst_cream->opcode_2 #define CRm inst_cream->crm @@ -3905,21 +3876,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } #endif - #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) - #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) - - #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((dst < lop) || (dst < rop))) - #define UPDATE_CFLAG_CARRY_FROM_ADD(lop, rop, flag) (cpu->CFlag = (((uint64_t) lop + (uint64_t) rop + (uint64_t) flag) > 0xffffffff) ) - #define UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(lop, rop, flag) (cpu->CFlag = ((uint64_t) lop >= ((uint64_t) rop + (uint64_t) flag))) - #define UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop) (cpu->CFlag = (lop >= rop)) - #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) (cpu->CFlag = !(dst < lop)) - #define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out) - - #define UPDATE_VFLAG(dst, lop, rop) (cpu->VFlag = (((lop < 0) && (rop < 0) && (dst >= 0)) || \ - ((lop >= 0) && (rop) >= 0 && (dst < 0)))) - #define UPDATE_VFLAG_WITH_NOT(dst, lop, rop) (cpu->VFlag = !(((lop < 0) && (rop < 0) && (dst >= 0)) || \ - ((lop >= 0) && (rop) >= 0 && (dst < 0)))) - #define UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop) (cpu->VFlag = (((lop ^ rop) & (lop ^ dst)) >> 31)) + #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) + #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) + #define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out) #define SAVE_NZCVT cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | \ (cpu->NFlag << 31) | \ @@ -3937,7 +3896,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { #define PC (cpu->Reg[15]) #define CHECK_EXT_INT if (!cpu->NirqSig && !(cpu->Cpsr & 0x80)) goto END; - arm_processor *cpu = state; + ARMul_State* cpu = state; // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback // to a clunky switch statement. @@ -3967,16 +3926,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) { &&INIT_INST_LENGTH,&&END }; #endif - arm_inst * inst_base; - unsigned int lop, rop, dst; + arm_inst* inst_base; unsigned int addr; unsigned int phys_addr; - unsigned int last_pc = 0; unsigned int num_instrs = 0; - static unsigned int last_physical_base = 0, last_logical_base = 0; int ptr; - bool single_step = (cpu->NumInstrsToExecute == 1); LOAD_NZCVT; DISPATCH: @@ -4003,16 +3958,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } ADC_INST: { - adc_inst *inst_cream = (adc_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - u32 left = RN; - u32 right = SHIFTER_OPERAND; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + adc_inst* const inst_cream = (adc_inst*)inst_base->component; - u64 unsigned_sum = (left + right + cpu->CFlag); - s64 signed_sum = (s64)(s32)left + (s64)(s32)right + (s64)cpu->CFlag; - u32 result = (unsigned_sum & 0xFFFFFFFF); + bool carry; + bool overflow; + RD = AddWithCarry(RN, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); - RD = result; if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -4020,10 +3972,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(result); - UPDATE_ZFLAG(result); - UPDATE_CFLAG_CARRY_FROM_ADD(left, right, cpu->CFlag); - cpu->VFlag = ((s64)(s32)result != signed_sum); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } if (inst_cream->Rd == 15) { INC_PC(sizeof(adc_inst)); @@ -4037,14 +3989,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } ADD_INST: { - add_inst *inst_cream = (add_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; - if (inst_cream->Rn == 15) { - lop += 2 * GET_INST_SIZE(cpu); - } - rop = SHIFTER_OPERAND; - RD = dst = lop + rop; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + add_inst* const inst_cream = (add_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * GET_INST_SIZE(cpu); + + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -4052,10 +4007,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - UPDATE_CFLAG(dst, lop, rop); - UPDATE_VFLAG((int)dst, (int)lop, (int)rop); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } if (inst_cream->Rd == 15) { INC_PC(sizeof(add_inst)); @@ -4071,9 +4026,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { { and_inst *inst_cream = (and_inst *)inst_base->component; if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; - rop = SHIFTER_OPERAND; - RD = dst = lop & rop; + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; + RD = lop & rop; if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -4081,8 +4036,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); UPDATE_CFLAG_WITH_SC; } if (inst_cream->Rd == 15) { @@ -4114,12 +4069,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) { { bic_inst *inst_cream = (bic_inst *)inst_base->component; if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; + u32 lop = RN; if (inst_cream->Rn == 15) { lop += 2 * GET_INST_SIZE(cpu); } - rop = SHIFTER_OPERAND; - RD = dst = lop & (~rop); + u32 rop = SHIFTER_OPERAND; + RD = lop & (~rop); if ((inst_cream->S) && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -4127,8 +4082,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); UPDATE_CFLAG_WITH_SC; } if (inst_cream->Rd == 15) { @@ -4142,6 +4097,16 @@ unsigned InterpreterMainLoop(ARMul_State* state) { GOTO_NEXT_INST; } BKPT_INST: + { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; + LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm); + } + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(bkpt_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } BLX_INST: { blx_inst *inst_cream = (blx_inst *)inst_base->component; @@ -4157,7 +4122,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu)); cpu->TFlag = 0x1; int signed_int = inst_cream->val.signed_immed_24; - signed_int = (signed_int) & 0x800000 ? (0x3F000000 | signed_int) : signed_int; + signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int; signed_int = signed_int << 2; cpu->Reg[15] = cpu->Reg[15] + 8 + signed_int + (BIT(inst, 24) << 1); } @@ -4177,8 +4142,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { // // According to the ARM documentation on BXJ, if setting the J bit in the APSR // fails, then BXJ functions identically like a regular BX instruction. - // - // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle. + // + // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle. if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { bx_inst* const inst_cream = (bx_inst*)inst_base->component; @@ -4199,8 +4164,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { CDP_INST: { - cdp_inst *inst_cream = (cdp_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { // Undefined instruction here cpu->NumInstrsToExecute = 0; return num_instrs; @@ -4223,8 +4187,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } CLZ_INST: { - clz_inst *inst_cream = (clz_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + clz_inst* inst_cream = (clz_inst*)inst_base->component; RD = clz(RM); } cpu->Reg[15] += GET_INST_SIZE(cpu); @@ -4234,15 +4198,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } CMN_INST: { - cmn_inst *inst_cream = (cmn_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; - rop = SHIFTER_OPERAND; - dst = lop + rop; - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - UPDATE_CFLAG(dst, lop, rop); - UPDATE_VFLAG((int)dst, (int)lop, (int)rop); + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + cmn_inst* const inst_cream = (cmn_inst*)inst_base->component; + + bool carry; + bool overflow; + u32 result = AddWithCarry(RN, SHIFTER_OPERAND, 0, &carry, &overflow); + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + cpu->CFlag = carry; + cpu->VFlag = overflow; } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(cmn_inst)); @@ -4251,19 +4217,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } CMP_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - cmp_inst *inst_cream = (cmp_inst *)inst_base->component; - lop = RN; - if (inst_cream->Rn == 15) { - lop += 2 * GET_INST_SIZE(cpu); - } - rop = SHIFTER_OPERAND; - dst = lop - rop; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + cmp_inst* const inst_cream = (cmp_inst*)inst_base->component; - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop); - UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop); + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * GET_INST_SIZE(cpu); + + bool carry; + bool overflow; + u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); + cpu->CFlag = carry; + cpu->VFlag = overflow; } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(cmp_inst)); @@ -4304,10 +4272,11 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } CPY_INST: { - mov_inst *inst_cream = (mov_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mov_inst* inst_cream = (mov_inst*)inst_base->component; + RD = SHIFTER_OPERAND; - if ((inst_cream->Rd == 15)) { + if (inst_cream->Rd == 15) { INC_PC(sizeof(mov_inst)); goto DISPATCH; } @@ -4319,14 +4288,15 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } EOR_INST: { - eor_inst *inst_cream = (eor_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + eor_inst* inst_cream = (eor_inst*)inst_base->component; + + u32 lop = RN; if (inst_cream->Rn == 15) { lop += 2 * GET_INST_SIZE(cpu); } - rop = SHIFTER_OPERAND; - RD = dst = lop ^ rop; + u32 rop = SHIFTER_OPERAND; + RD = lop ^ rop; if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -4334,8 +4304,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); UPDATE_CFLAG_WITH_SC; } if (inst_cream->Rd == 15) { @@ -4359,8 +4329,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDM_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); unsigned int inst = inst_cream->inst; @@ -4429,8 +4399,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SXTH_INST: { - sxth_inst *inst_cream = (sxth_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxth_inst* inst_cream = (sxth_inst*)inst_base->component; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); if (BIT(operand2, 15)) { operand2 |= 0xffff0000; @@ -4451,12 +4422,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); unsigned int value = Memory::Read32(addr); - if (BIT(CP15_REG(CP15_CONTROL), 22) == 1) - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - else { - value = ROTATE_RIGHT_32(value,(8*(addr&0x3))); - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - } + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; if (BITS(inst_cream->inst, 12, 15) == 15) { // For armv5t, should enter thumb when bits[0] is non-zero. @@ -4474,16 +4440,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRCOND_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; if (CondPassed(cpu, inst_base->cond)) { + ldst_inst *inst_cream = (ldst_inst *)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + unsigned int value = Memory::Read32(addr); - if (BIT(CP15_REG(CP15_CONTROL), 22) == 1) - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - else { - value = ROTATE_RIGHT_32(value,(8*(addr&0x3))); - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - } + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; if (BITS(inst_cream->inst, 12, 15) == 15) { // For armv5t, should enter thumb when bits[0] is non-zero. @@ -4500,11 +4462,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } UXTH_INST: { - uxth_inst *inst_cream = (uxth_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) - & 0xffff; - RD = operand2; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxth_inst* inst_cream = (uxth_inst*)inst_base->component; + RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(uxth_inst)); @@ -4513,10 +4473,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } UXTAH_INST: { - uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) - & 0xffff; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component; + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; + RD = RN + operand2; if (inst_cream->Rn == 15 || inst_cream->Rm == 15) { LOG_ERROR(Core_ARM11, "invalid operands for UXTAH"); @@ -4530,9 +4490,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRB_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr); if (BITS(inst_cream->inst, 12, 15) == 15) { @@ -4547,9 +4508,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRBT_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr); if (BITS(inst_cream->inst, 12, 15) == 15) { @@ -4564,8 +4526,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRD_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0) inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); @@ -4582,8 +4544,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LDREX_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int read_addr = RN; add_exclusive_addr(cpu, read_addr); @@ -4602,8 +4564,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDREXB_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int read_addr = RN; add_exclusive_addr(cpu, read_addr); @@ -4622,8 +4584,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDREXH_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int read_addr = RN; add_exclusive_addr(cpu, read_addr); @@ -4642,8 +4604,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDREXD_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int read_addr = RN; add_exclusive_addr(cpu, read_addr); @@ -4664,8 +4626,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRH_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read16(addr); if (BITS(inst_cream->inst, 12, 15) == 15) { @@ -4680,8 +4642,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRSB_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); unsigned int value = Memory::Read8(addr); if (BIT(value, 7)) { @@ -4700,8 +4662,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRSH_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); unsigned int value = Memory::Read16(addr); if (BIT(value, 15)) { @@ -4720,17 +4682,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } LDRT_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 1); + unsigned int value = Memory::Read32(addr); cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - if (BIT(CP15_REG(CP15_CONTROL), 22) == 1) - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; - else - cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ROTATE_RIGHT_32(value,(8*(addr&0x3))) ; - if (BITS(inst_cream->inst, 12, 15) == 15) { INC_PC(sizeof(ldst_inst)); goto DISPATCH; @@ -4743,8 +4701,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } MCR_INST: { - mcr_inst *inst_cream = (mcr_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mcr_inst* inst_cream = (mcr_inst*)inst_base->component; + unsigned int inst = inst_cream->inst; if (inst_cream->Rd == 15) { DEBUG_MSG; @@ -4752,20 +4711,20 @@ unsigned InterpreterMainLoop(ARMul_State* state) { if (inst_cream->cp_num == 15) { if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { CP15_REG(CP15_MAIN_ID) = RD; + } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) { + CP15_REG(CP15_CONTROL) = RD; } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) { CP15_REG(CP15_AUXILIARY_CONTROL) = RD; } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) { CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD; - } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) { - CP15_REG(CP15_CONTROL) = RD; - } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) { - CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD; } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) { CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD; } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) { CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD; } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) { CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD; + } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) { + CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD; } else if(CRn == MMU_CACHE_OPS){ //LOG_WARNING(Core_ARM11, "cache operations have not implemented."); } else if(CRn == MMU_TLB_OPS){ @@ -4820,12 +4779,18 @@ unsigned InterpreterMainLoop(ARMul_State* state) { break; } } else if(CRn == MMU_PID) { - if(OPCODE_2 == 0) + if(OPCODE_2 == 0) { CP15_REG(CP15_PID) = RD; - else if(OPCODE_2 == 1) + } else if(OPCODE_2 == 1) { CP15_REG(CP15_CONTEXT_ID) = RD; - else if(OPCODE_2 == 3) { - CP15_REG(CP15_THREAD_URO) = RD; + } else if (OPCODE_2 == 2) { + CP15_REG(CP15_THREAD_UPRW) = RD; + } else if(OPCODE_2 == 3) { + if (InAPrivilegedMode(cpu)) + CP15_REG(CP15_THREAD_URO) = RD; + } else if (OPCODE_2 == 4) { + if (InAPrivilegedMode(cpu)) + CP15_REG(CP15_THREAD_PRW) = RD; } else { LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn); } @@ -4843,8 +4808,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { MCRR_INST: MLA_INST: { - mla_inst *inst_cream = (mla_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mla_inst* inst_cream = (mla_inst*)inst_base->component; + uint64_t rm = RM; uint64_t rs = RS; uint64_t rn = RN; @@ -4852,10 +4818,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOG_ERROR(Core_ARM11, "invalid operands for MLA"); CITRA_IGNORE_EXIT(-1); } - RD = dst = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff); + RD = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff); if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); } if (inst_cream->Rd == 15) { INC_PC(sizeof(mla_inst)); @@ -4869,9 +4835,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } MOV_INST: { - mov_inst *inst_cream = (mov_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - RD = dst = SHIFTER_OPERAND; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mov_inst* inst_cream = (mov_inst*)inst_base->component; + + RD = SHIFTER_OPERAND; if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -4879,8 +4846,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); UPDATE_CFLAG_WITH_SC; } if (inst_cream->Rd == 15) { @@ -4895,8 +4862,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } MRC_INST: { - mrc_inst *inst_cream = (mrc_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mrc_inst* inst_cream = (mrc_inst*)inst_base->component; + unsigned int inst = inst_cream->inst; if (inst_cream->Rd == 15) { DEBUG_MSG; @@ -4910,31 +4878,40 @@ unsigned InterpreterMainLoop(ARMul_State* state) { if (inst_cream->cp_num == 15) { if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { RD = cpu->CP15[CP15(CP15_MAIN_ID)]; + } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) { + RD = cpu->CP15[CP15(CP15_CACHE_TYPE)]; } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) { RD = cpu->CP15[CP15(CP15_CONTROL)]; } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) { RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)]; } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) { RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)]; - } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) { - RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)]; } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) { RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)]; + } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) { + RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)]; + } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) { + RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)]; + } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) { + RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)]; } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) { RD = cpu->CP15[CP15(CP15_FAULT_STATUS)]; - } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) { - RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)]; - } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) { - RD = cpu->CP15[CP15(CP15_CACHE_TYPE)]; } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) { RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)]; + } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) { + RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)]; } else if (CRn == 13) { - if(OPCODE_2 == 0) + if(OPCODE_2 == 0) { RD = CP15_REG(CP15_PID); - else if(OPCODE_2 == 1) + } else if(OPCODE_2 == 1) { RD = CP15_REG(CP15_CONTEXT_ID); - else if(OPCODE_2 == 3) { + } else if (OPCODE_2 == 2) { + RD = CP15_REG(CP15_THREAD_UPRW); + } else if(OPCODE_2 == 3) { RD = Memory::KERNEL_MEMORY_VADDR; + } else if (OPCODE_2 == 4) { + if (InAPrivilegedMode(cpu)) + RD = CP15_REG(CP15_THREAD_PRW); } else { LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn); } @@ -4952,8 +4929,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { MRRC_INST: MRS_INST: { - mrs_inst *inst_cream = (mrs_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mrs_inst* inst_cream = (mrs_inst*)inst_base->component; + if (inst_cream->R) { RD = cpu->Spsr_copy; } else { @@ -4969,7 +4947,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { MSR_INST: { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { - msr_inst *inst_cream = (msr_inst *)inst_base->component; + msr_inst* inst_cream = (msr_inst*)inst_base->component; const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; unsigned int inst = inst_cream->inst; unsigned int operand; @@ -4982,7 +4960,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0) | (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0); - uint32_t mask; + uint32_t mask = 0; if (!inst_cream->R) { if (InAPrivilegedMode(cpu)) { if ((operand & StateMask) != 0) { @@ -5012,14 +4990,15 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } MUL_INST: { - mul_inst *inst_cream = (mul_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mul_inst* inst_cream = (mul_inst*)inst_base->component; + uint64_t rm = RM; uint64_t rs = RS; - RD = dst = static_cast<uint32_t>((rm * rs) & 0xffffffff); + RD = static_cast<uint32_t>((rm * rs) & 0xffffffff); if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); } if (inst_cream->Rd == 15) { INC_PC(sizeof(mul_inst)); @@ -5033,9 +5012,11 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } MVN_INST: { - mvn_inst *inst_cream = (mvn_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - RD = dst = ~SHIFTER_OPERAND; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + mvn_inst* const inst_cream = (mvn_inst*)inst_base->component; + + RD = ~SHIFTER_OPERAND; + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -5043,8 +5024,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); UPDATE_CFLAG_WITH_SC; } if (inst_cream->Rd == 15) { @@ -5059,11 +5040,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } ORR_INST: { - orr_inst *inst_cream = (orr_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; - rop = SHIFTER_OPERAND; - RD = dst = lop | rop; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + orr_inst* const inst_cream = (orr_inst*)inst_base->component; + + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; + RD = lop | rop; + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -5071,8 +5054,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); UPDATE_CFLAG_WITH_SC; } if (inst_cream->Rd == 15) { @@ -5292,14 +5275,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) { RFE_INST: RSB_INST: { - rsb_inst *inst_cream = (rsb_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - rop = RN; - lop = SHIFTER_OPERAND; - if (inst_cream->Rn == 15) { - rop += 2 * GET_INST_SIZE(cpu);; - } - RD = dst = lop - rop; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + rsb_inst* const inst_cream = (rsb_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 2 * GET_INST_SIZE(cpu); + + bool carry; + bool overflow; + RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow); + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -5307,10 +5293,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop); - UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } if (inst_cream->Rd == 15) { INC_PC(sizeof(rsb_inst)); @@ -5324,11 +5310,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } RSC_INST: { - rsc_inst *inst_cream = (rsc_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; - rop = SHIFTER_OPERAND; - RD = dst = rop - lop - !cpu->CFlag; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + rsc_inst* const inst_cream = (rsc_inst*)inst_base->component; + + bool carry; + bool overflow; + RD = AddWithCarry(~RN, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -5336,10 +5324,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(rop, lop, !cpu->CFlag); - UPDATE_VFLAG_OVERFLOW_FROM((int)dst, (int)rop, (int)lop); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } if (inst_cream->Rd == 15) { INC_PC(sizeof(rsc_inst)); @@ -5462,11 +5450,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SBC_INST: { - sbc_inst *inst_cream = (sbc_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = SHIFTER_OPERAND + !cpu->CFlag; - rop = RN; - RD = dst = rop - lop; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sbc_inst* const inst_cream = (sbc_inst*)inst_base->component; + + bool carry; + bool overflow; + RD = AddWithCarry(RN, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -5474,15 +5464,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - - if(rop >= !cpu->CFlag) - UPDATE_CFLAG_NOT_BORROW_FROM(rop - !cpu->CFlag, SHIFTER_OPERAND); - else - UPDATE_CFLAG_NOT_BORROW_FROM(rop, !cpu->CFlag); - - UPDATE_VFLAG_OVERFLOW_FROM(dst, rop, lop); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } if (inst_cream->Rd == 15) { INC_PC(sizeof(sbc_inst)); @@ -5610,8 +5595,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SMLA_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - smla_inst *inst_cream = (smla_inst *)inst_base->component; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smla_inst* inst_cream = (smla_inst*)inst_base->component; int32_t operand1, operand2; if (inst_cream->x == 0) operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); @@ -5691,8 +5676,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SMLAL_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - umlal_inst *inst_cream = (umlal_inst *)inst_base->component; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; long long int rm = RM; long long int rs = RS; if (BIT(rm, 31)) { @@ -5849,8 +5834,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SMUL_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - smul_inst *inst_cream = (smul_inst *)inst_base->component; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smul_inst* inst_cream = (smul_inst*)inst_base->component; uint32_t operand1, operand2; if (inst_cream->x == 0) operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15); @@ -5870,8 +5855,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SMULL_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - umull_inst *inst_cream = (umull_inst *)inst_base->component; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umull_inst* inst_cream = (umull_inst*)inst_base->component; int64_t rm = RM; int64_t rs = RS; if (BIT(rm, 31)) { @@ -5979,9 +5964,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STM_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - unsigned int inst = inst_cream->inst; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; + unsigned int inst = inst_cream->inst; + int i; unsigned int Rn = BITS(inst, 16, 19); unsigned int old_RN = cpu->Reg[Rn]; @@ -6039,8 +6025,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SXTB_INST: { - sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; + if (inst_cream->Rm == 15) { LOG_ERROR(Core_ARM11, "invalid operand for SXTB"); CITRA_IGNORE_EXIT(-1); @@ -6059,9 +6046,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STR_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; Memory::Write32(addr, value); } @@ -6072,11 +6060,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } UXTB_INST: { - uxtb_inst *inst_cream = (uxtb_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) - & 0xff; - RD = operand2; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component; + RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(uxtb_inst)); @@ -6085,10 +6071,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } UXTAB_INST: { - uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) - & 0xff; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component; + + unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; RD = RN + operand2; } cpu->Reg[15] += GET_INST_SIZE(cpu); @@ -6098,8 +6084,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STRB_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; Memory::Write8(addr, value); @@ -6111,8 +6097,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STRBT_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; Memory::Write8(addr, value); @@ -6124,8 +6110,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STRD_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; @@ -6140,9 +6126,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STREX_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int write_addr = cpu->Reg[inst_cream->Rn]; if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { @@ -6163,9 +6148,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STREXB_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int write_addr = cpu->Reg[inst_cream->Rn]; if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { @@ -6186,9 +6170,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STREXD_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int write_addr = cpu->Reg[inst_cream->Rn]; if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { @@ -6211,9 +6194,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STREXH_INST: { - generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; - - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; unsigned int write_addr = cpu->Reg[inst_cream->Rn]; if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) { @@ -6234,9 +6216,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STRH_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; Memory::Write16(addr, value); } @@ -6247,9 +6230,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } STRT_INST: { - ldst_inst *inst_cream = (ldst_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr, 0); + unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; Memory::Write32(addr, value); } @@ -6260,14 +6244,17 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SUB_INST: { - sub_inst *inst_cream = (sub_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - lop = RN; - if (inst_cream->Rn == 15) { - lop += 8; - } - rop = SHIFTER_OPERAND; - RD = dst = lop - rop; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sub_inst* const inst_cream = (sub_inst*)inst_base->component; + + u32 rn_val = RN; + if (inst_cream->Rn == 15) + rn_val += 8; + + bool carry; + bool overflow; + RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); + if (inst_cream->S && (inst_cream->Rd == 15)) { if (CurrentModeHasSPSR) { cpu->Cpsr = cpu->Spsr_copy; @@ -6275,10 +6262,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { LOAD_NZCVT; } } else if (inst_cream->S) { - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); - UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop); - UPDATE_VFLAG_OVERFLOW_FROM(dst, lop, rop); + UPDATE_NFLAG(RD); + UPDATE_ZFLAG(RD); + cpu->CFlag = carry; + cpu->VFlag = overflow; } if (inst_cream->Rd == 15) { INC_PC(sizeof(sub_inst)); @@ -6292,10 +6279,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SWI_INST: { - swi_inst *inst_cream = (swi_inst *)inst_base->component; - - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { HLE::CallSVC(Memory::Read32(cpu->Reg[15])); + } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(swi_inst)); @@ -6304,8 +6290,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SWP_INST: { - swp_inst *inst_cream = (swp_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + swp_inst* inst_cream = (swp_inst*)inst_base->component; + addr = RN; unsigned int value; value = Memory::Read32(addr); @@ -6320,8 +6307,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SWPB_INST: { - swp_inst *inst_cream = (swp_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + swp_inst* inst_cream = (swp_inst*)inst_base->component; addr = RN; unsigned int value = Memory::Read8(addr); Memory::Write8(addr, (RM & 0xFF)); @@ -6334,8 +6321,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SXTAB_INST: { - sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component; + // R15 should be check if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15){ CITRA_IGNORE_EXIT(-1); @@ -6387,8 +6375,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SXTAH_INST: { - sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component; - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component; + // R15 should be check if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15) { CITRA_IGNORE_EXIT(-1); @@ -6406,18 +6395,19 @@ unsigned InterpreterMainLoop(ARMul_State* state) { TEQ_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - teq_inst *inst_cream = (teq_inst *)inst_base->component; - lop = RN; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + teq_inst* const inst_cream = (teq_inst*)inst_base->component; + + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; if (inst_cream->Rn == 15) lop += GET_INST_SIZE(cpu) * 2; - rop = SHIFTER_OPERAND; - dst = lop ^ rop; + u32 result = lop ^ rop; - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); UPDATE_CFLAG_WITH_SC; } cpu->Reg[15] += GET_INST_SIZE(cpu); @@ -6427,18 +6417,19 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } TST_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - tst_inst *inst_cream = (tst_inst *)inst_base->component; - lop = RN; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + tst_inst* const inst_cream = (tst_inst*)inst_base->component; + + u32 lop = RN; + u32 rop = SHIFTER_OPERAND; if (inst_cream->Rn == 15) lop += GET_INST_SIZE(cpu) * 2; - rop = SHIFTER_OPERAND; - dst = lop & rop; + u32 result = lop & rop; - UPDATE_NFLAG(dst); - UPDATE_ZFLAG(dst); + UPDATE_NFLAG(result); + UPDATE_ZFLAG(result); UPDATE_CFLAG_WITH_SC; } cpu->Reg[15] += GET_INST_SIZE(cpu); @@ -6718,8 +6709,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } UMLAL_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - umlal_inst *inst_cream = (umlal_inst *)inst_base->component; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umlal_inst* inst_cream = (umlal_inst*)inst_base->component; unsigned long long int rm = RM; unsigned long long int rs = RS; unsigned long long int rst = rm * rs; @@ -6741,8 +6732,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } UMULL_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - umull_inst *inst_cream = (umull_inst *)inst_base->component; + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + umull_inst* inst_cream = (umull_inst*)inst_base->component; unsigned long long int rm = RM; unsigned long long int rs = RS; unsigned long long int rst = rm * rs; @@ -6761,14 +6752,14 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } B_2_THUMB: { - b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component; + b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component; cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; INC_PC(sizeof(b_2_thumb)); goto DISPATCH; } B_COND_THUMB: { - b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component; + b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component; if(CondPassed(cpu, inst_cream->cond)) cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; @@ -6780,7 +6771,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } BL_1_THUMB: { - bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component; + bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component; cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm; cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(bl_1_thumb)); @@ -6789,7 +6780,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } BL_2_THUMB: { - bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component; + bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component; int tmp = ((cpu->Reg[15] + 2) | 1); cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm); cpu->Reg[14] = tmp; @@ -6800,7 +6791,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { { // BLX 1 for armv5t and above u32 tmp = cpu->Reg[15]; - blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component; + blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component; cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC; cpu->Reg[14] = ((tmp + 2) | 1); cpu->TFlag = 0; diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.h b/src/core/arm/dyncom/arm_dyncom_interpreter.h index 4791ea25f..1c324d29c 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.h +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.h @@ -4,4 +4,6 @@ #pragma once +#include "core/arm/skyeye_common/armdefs.h" + unsigned InterpreterMainLoop(ARMul_State* state); diff --git a/src/core/arm/dyncom/arm_dyncom_run.cpp b/src/core/arm/dyncom/arm_dyncom_run.cpp index d457d0ac5..5a9a6a788 100644 --- a/src/core/arm/dyncom/arm_dyncom_run.cpp +++ b/src/core/arm/dyncom/arm_dyncom_run.cpp @@ -2,16 +2,16 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. -#include <assert.h> - +#include "core/arm/dyncom/arm_dyncom_run.h" #include "core/arm/skyeye_common/armdefs.h" -void switch_mode(arm_core_t *core, uint32_t mode) { +void switch_mode(ARMul_State* core, uint32_t mode) { if (core->Mode == mode) return; if (mode != USERBANK) { switch (core->Mode) { + case SYSTEM32MODE: // Shares registers with user mode case USER32MODE: core->Reg_usr[0] = core->Reg[13]; core->Reg_usr[1] = core->Reg[14]; @@ -41,7 +41,6 @@ void switch_mode(arm_core_t *core, uint32_t mode) { core->Reg_firq[1] = core->Reg[14]; core->Spsr[FIQBANK] = core->Spsr_copy; break; - } switch (mode) { @@ -80,11 +79,15 @@ void switch_mode(arm_core_t *core, uint32_t mode) { core->Spsr_copy = core->Spsr[FIQBANK]; core->Bank = FIQBANK; break; - + case SYSTEM32MODE: // Shares registers with user mode. + core->Reg[13] = core->Reg_usr[0]; + core->Reg[14] = core->Reg_usr[1]; + core->Bank = SYSTEMBANK; + break; } + + // Set the mode bits in the APSR + core->Cpsr = (core->Cpsr & ~core->Mode) | mode; core->Mode = mode; - } else { - LOG_CRITICAL(Core_ARM11, "user mode"); - exit(-2); } } diff --git a/src/core/arm/dyncom/arm_dyncom_run.h b/src/core/arm/dyncom/arm_dyncom_run.h index c70522274..e17420497 100644 --- a/src/core/arm/dyncom/arm_dyncom_run.h +++ b/src/core/arm/dyncom/arm_dyncom_run.h @@ -16,15 +16,14 @@ * */ -#ifndef __ARM_DYNCOM_RUN__ -#define __ARM_DYNCOM_RUN__ +#pragma once -#include "core/arm/skyeye_common/skyeye_types.h" +#include "core/arm/skyeye_common/armdefs.h" -void switch_mode(arm_core_t *core, uint32_t mode); +void switch_mode(ARMul_State* core, uint32_t mode); /* FIXME, we temporarily think thumb instruction is always 16 bit */ -static inline u32 GET_INST_SIZE(arm_core_t* core) { +static inline u32 GET_INST_SIZE(ARMul_State* core) { return core->TFlag? 2 : 4; } @@ -36,7 +35,7 @@ static inline u32 GET_INST_SIZE(arm_core_t* core) { * * @return */ -static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) { +static inline addr_t CHECK_READ_REG15_WA(ARMul_State* core, int Rn) { return (Rn == 15)? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; } @@ -48,8 +47,6 @@ static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) { * * @return */ -static inline u32 CHECK_READ_REG15(arm_core_t* core, int Rn) { +static inline u32 CHECK_READ_REG15(ARMul_State* core, int Rn) { return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; } - -#endif diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index de70ca8ae..e30d515fb 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp @@ -5,27 +5,17 @@ // We can provide simple Thumb simulation by decoding the Thumb instruction into its corresponding // ARM instruction, and using the existing ARM simulator. -#include "core/arm/skyeye_common/skyeye_defs.h" - -#ifndef MODET // Required for the Thumb instruction support -#if 1 -#error "MODET needs to be defined for the Thumb world to work" -#else -#define MODET (1) -#endif -#endif - -#include "core/arm/skyeye_common/armos.h" #include "core/arm/dyncom/arm_dyncom_thumb.h" +#include "core/arm/skyeye_common/armos.h" +#include "core/arm/skyeye_common/skyeye_defs.h" // Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field, // with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions // allows easier simulation of the special dual BL instruction. -tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) { +tdstate thumb_translate(addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) { tdstate valid = t_uninitialized; - ARMword tinstr; - tinstr = instr; + ARMword tinstr = instr; // The endian should be judge here if((addr & 0x3) != 0) @@ -48,7 +38,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t case 3: // ADD/SUB { - ARMword subset[4] = { + static const ARMword subset[4] = { 0xE0900000, // ADDS Rd,Rs,Rn 0xE0500000, // SUBS Rd,Rs,Rn 0xE2900000, // ADDS Rd,Rs,#imm3 @@ -67,7 +57,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t case 6: // ADD case 7: // SUB { - ARMword subset[4] = { + static const ARMword subset[4] = { 0xE3B00000, // MOVS Rd,#imm8 0xE3500000, // CMP Rd,#imm8 0xE2900000, // ADDS Rd,Rd,#imm8 @@ -95,7 +85,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t t_mul }; - struct { + static const struct { ARMword opcode; otype type; } subset[16] = { @@ -205,7 +195,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t // merged into a single subset, saving on the following boolean: if ((tinstr & (1 << 9)) == 0) { - ARMword subset[4] = { + static const ARMword subset[4] = { 0xE7800000, // STR Rd,[Rb,Ro] 0xE7C00000, // STRB Rd,[Rb,Ro] 0xE7900000, // LDR Rd,[Rb,Ro] @@ -218,7 +208,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t |((tinstr & 0x01C0) >> 6); // Ro } else { - ARMword subset[4] = { + static const ARMword subset[4] = { 0xE18000B0, // STRH Rd,[Rb,Ro] 0xE19000D0, // LDRSB Rd,[Rb,Ro] 0xE19000B0, // LDRH Rd,[Rb,Ro] @@ -236,7 +226,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t case 14: // STRB Rd,[Rb,#imm5] case 15: // LDRB Rd,[Rb,#imm5] { - ARMword subset[4] = { + static const ARMword subset[4] = { 0xE5800000, // STR Rd,[Rb,#imm5] 0xE5900000, // LDR Rd,[Rb,#imm5] 0xE5C00000, // STRB Rd,[Rb,#imm5] @@ -300,7 +290,7 @@ tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t } else if ((tinstr & 0x0F00) == 0x0e00) *ainstr = 0xEF000000 | SWI_Breakpoint; else { - ARMword subset[4] = { + static const ARMword subset[4] = { 0xE92D0000, // STMDB sp!,{rlist} 0xE92D4000, // STMDB sp!,{rlist,lr} 0xE8BD0000, // LDMIA sp!,{rlist} diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h index bf69b2fd4..a1785abb8 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.h +++ b/src/core/arm/dyncom/arm_dyncom_thumb.h @@ -24,11 +24,9 @@ * @date 2011-11-07 */ -#ifndef __ARM_DYNCOM_THUMB_H__ -#define __ARM_DYNCOM_THUMB_H__ +#pragma once #include "core/arm/skyeye_common/armdefs.h" -#include "core/arm/skyeye_common/skyeye_types.h" enum tdstate { t_undefined, // Undefined Thumb instruction @@ -47,5 +45,3 @@ static inline u32 get_thumb_instr(u32 instr, addr_t pc) { tinstr = instr & 0xFFFF; return tinstr; } - -#endif |