diff options
| author | bunnei <bunneidev@gmail.com> | 2014-12-23 09:43:46 -0500 |
|---|---|---|
| committer | bunnei <bunneidev@gmail.com> | 2014-12-23 09:43:46 -0500 |
| commit | 53447da142e4466fc2e509d19c15423ba7595fac (patch) | |
| tree | ba4f97d9efd0db16d14e49e42f71a6365dd531fe /src/core/arm/interpreter/armsupp.cpp | |
| parent | 949d95659e019d2c1bb58327827e1a9fc39b28ee (diff) | |
| parent | 6446331938c4d7c5bc4f54bc2b973b3eb43d7852 (diff) | |
Merge pull request #335 from lioncash/cpsrcreate
armemu: Emulate the GE and Q flags.
Diffstat (limited to 'src/core/arm/interpreter/armsupp.cpp')
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index 30519f216..b31c0ea24 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp @@ -227,8 +227,9 @@ ARMul_CPSRAltered (ARMul_State * state) //state->Cpsr &= ~CBIT; ASSIGNV ((state->Cpsr & VBIT) != 0); //state->Cpsr &= ~VBIT; - ASSIGNS ((state->Cpsr & SBIT) != 0); - //state->Cpsr &= ~SBIT; + ASSIGNQ ((state->Cpsr & QBIT) != 0); + //state->Cpsr &= ~QBIT; + state->GEFlag = (state->Cpsr & 0x000F0000); #ifdef MODET ASSIGNT ((state->Cpsr & TBIT) != 0); //state->Cpsr &= ~TBIT; |