From 2be8b6ea4527239fff1b2fdf9dc7ce1346b173e6 Mon Sep 17 00:00:00 2001
From: Domenico V <35856442+LDj3SNuD@users.noreply.github.com>
Date: Mon, 31 Jul 2023 01:57:37 +0200
Subject: CPU (A64): Add Fmaxp & Fminp Scalar Inst.s, Fast & Slow Paths; with
 Tests. (#5502)

* Add Fmaxp & Fminp Scalar Inst.s, Fast & Slow Paths; with Tests.

* Ptc.InternalVersion = 5502
---
 .../Instructions/InstEmitSimdArithmetic.cs         | 50 ++++++++++++++++++++++
 1 file changed, 50 insertions(+)

(limited to 'src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs')

diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
index 7b308fa9..543aab02 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
@@ -883,6 +883,31 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        public static void Fmaxp_S(ArmEmitterContext context)
+        {
+            if (Optimizations.UseAdvSimd)
+            {
+                InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FmaxpS);
+            }
+            else if (Optimizations.FastFP && Optimizations.UseSse41)
+            {
+                EmitSse2ScalarPairwiseOpF(context, (op1, op2) =>
+                {
+                    return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
+                    {
+                        return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: true);
+                    }, scalar: true, op1, op2);
+                });
+            }
+            else
+            {
+                EmitScalarPairwiseOpF(context, (op1, op2) =>
+                {
+                    return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMax), op1, op2);
+                });
+            }
+        }
+
         public static void Fmaxp_V(ArmEmitterContext context)
         {
             if (Optimizations.UseAdvSimd)
@@ -1081,6 +1106,31 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        public static void Fminp_S(ArmEmitterContext context)
+        {
+            if (Optimizations.UseAdvSimd)
+            {
+                InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FminpS);
+            }
+            else if (Optimizations.FastFP && Optimizations.UseSse41)
+            {
+                EmitSse2ScalarPairwiseOpF(context, (op1, op2) =>
+                {
+                    return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
+                    {
+                        return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: false);
+                    }, scalar: true, op1, op2);
+                });
+            }
+            else
+            {
+                EmitScalarPairwiseOpF(context, (op1, op2) =>
+                {
+                    return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMin), op1, op2);
+                });
+            }
+        }
+
         public static void Fminp_V(ArmEmitterContext context)
         {
             if (Optimizations.UseAdvSimd)
-- 
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