From cee712105850ac3385cd0091a923438167433f9f Mon Sep 17 00:00:00 2001
From: TSR Berry <20988865+TSRBerry@users.noreply.github.com>
Date: Sat, 8 Apr 2023 01:22:00 +0200
Subject: Move solution and projects to src

---
 src/ARMeilleure/Decoders/OpCode32SimdExt.cs | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 src/ARMeilleure/Decoders/OpCode32SimdExt.cs

(limited to 'src/ARMeilleure/Decoders/OpCode32SimdExt.cs')

diff --git a/src/ARMeilleure/Decoders/OpCode32SimdExt.cs b/src/ARMeilleure/Decoders/OpCode32SimdExt.cs
new file mode 100644
index 00000000..6dbb5b66
--- /dev/null
+++ b/src/ARMeilleure/Decoders/OpCode32SimdExt.cs
@@ -0,0 +1,20 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCode32SimdExt : OpCode32SimdReg
+    {
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode, true);
+
+        public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
+        {
+            Immediate = (opCode >> 8) & 0xf;
+            Size = 0;
+            if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm, Vn) || (!Q && Immediate > 7))
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
+        }
+    }
+}
-- 
cgit v1.2.3