From cee712105850ac3385cd0091a923438167433f9f Mon Sep 17 00:00:00 2001
From: TSR Berry <20988865+TSRBerry@users.noreply.github.com>
Date: Sat, 8 Apr 2023 01:22:00 +0200
Subject: Move solution and projects to src

---
 src/ARMeilleure/Decoders/OpCode32MsrReg.cs | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 src/ARMeilleure/Decoders/OpCode32MsrReg.cs

(limited to 'src/ARMeilleure/Decoders/OpCode32MsrReg.cs')

diff --git a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs
new file mode 100644
index 00000000..d897ffd8
--- /dev/null
+++ b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs
@@ -0,0 +1,29 @@
+using ARMeilleure.State;
+
+namespace ARMeilleure.Decoders
+{
+    class OpCode32MsrReg : OpCode32
+    {
+        public bool R      { get; }
+        public int  Mask   { get; }
+        public int  Rd     { get; }
+        public bool Banked { get; }
+        public int  Rn     { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode);
+
+        public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            R = ((opCode >> 22) & 1) != 0;
+            Mask = (opCode >> 16) & 0xf;
+            Rd = (opCode >> 12) & 0xf;
+            Banked = ((opCode >> 9) & 1) != 0;
+            Rn = (opCode >> 0) & 0xf;
+
+            if (Rn == RegisterAlias.Aarch32Pc || Mask == 0)
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
+        }
+    }
+}
-- 
cgit v1.2.3