From cee712105850ac3385cd0091a923438167433f9f Mon Sep 17 00:00:00 2001
From: TSR Berry <20988865+TSRBerry@users.noreply.github.com>
Date: Sat, 8 Apr 2023 01:22:00 +0200
Subject: Move solution and projects to src

---
 src/ARMeilleure/Decoders/OpCode32AluMla.cs | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 src/ARMeilleure/Decoders/OpCode32AluMla.cs

(limited to 'src/ARMeilleure/Decoders/OpCode32AluMla.cs')

diff --git a/src/ARMeilleure/Decoders/OpCode32AluMla.cs b/src/ARMeilleure/Decoders/OpCode32AluMla.cs
new file mode 100644
index 00000000..2cd2b9dc
--- /dev/null
+++ b/src/ARMeilleure/Decoders/OpCode32AluMla.cs
@@ -0,0 +1,30 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCode32AluMla : OpCode32, IOpCode32AluMla
+    {
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Ra { get; }
+        public int Rd { get; }
+
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+        public bool R { get; }
+        public bool? SetFlags { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
+
+        public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rn = (opCode >> 0) & 0xf;
+            Rm = (opCode >> 8) & 0xf;
+            Ra = (opCode >> 12) & 0xf;
+            Rd = (opCode >> 16) & 0xf;
+            R = (opCode & (1 << 5)) != 0;
+
+            NHigh = ((opCode >> 5) & 0x1) == 1;
+            MHigh = ((opCode >> 6) & 0x1) == 1;
+            SetFlags = ((opCode >> 20) & 1) != 0;
+        }
+    }
+}
-- 
cgit v1.2.3