From e5f7ff1eee81ebc852b8bc703d5f4847eb430560 Mon Sep 17 00:00:00 2001 From: sharmander Date: Tue, 4 Jan 2022 14:45:28 -0500 Subject: CPU - Implement FCVTMS (Vector) (#2937) * Add FCVTMS_V Implementation to Armeilleure * Fix opcode designation * Add tests * Amend Ptc version * Fix OpCode / Tests * Create Math.Floor helper method + Update implementation * Address gdk comments * Re-address gdk comments * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: gdkchan * Update Tests to use 2S (4S) and 2D Co-authored-by: gdkchan --- Ryujinx.Tests/Cpu/CpuTestSimd.cs | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Ryujinx.Tests/Cpu') diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 89c28570..c20e11ee 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -865,6 +865,7 @@ namespace Ryujinx.Tests.Cpu { 0x0E21C800u, // FCVTAS V0.2S, V0.2S 0x2E21C800u, // FCVTAU V0.2S, V0.2S + 0x0E21B800u, // FCVTMS V0.2S, V0.2S 0x0E21A800u, // FCVTNS V0.2S, V0.2S 0x2E21A800u, // FCVTNU V0.2S, V0.2S 0x0EA1B800u, // FCVTZS V0.2S, V0.2S @@ -878,6 +879,7 @@ namespace Ryujinx.Tests.Cpu { 0x4E61C800u, // FCVTAS V0.2D, V0.2D 0x6E61C800u, // FCVTAU V0.2D, V0.2D + 0x4E61B800u, // FCVTMS V0.2D, V0.2D 0x4E61A800u, // FCVTNS V0.2D, V0.2D 0x6E61A800u, // FCVTNU V0.2D, V0.2D 0x4EE1B800u, // FCVTZS V0.2D, V0.2D -- cgit v1.2.3