From 9bda7b469946dc44e4ee625ea69494da215c57aa Mon Sep 17 00:00:00 2001
From: mageven <62494521+mageven@users.noreply.github.com>
Date: Mon, 22 Feb 2021 20:56:13 +0530
Subject: Implement VCNT instruction (#1963)

* Implement VCNT based on AArch64 CNT

Add tests

* Update PTC version

* Address LDj's comments

* Explicit size in encoding
* Tighter tests
* Replace SoftFallback with IR helper

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

* Reduce one BitwiseAnd from IR fallback

Based on popcount64b from https://en.wikipedia.org/wiki/Hamming_weight#Efficient_implementation

* Rename parameter and add assert

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>

Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
---
 Ryujinx.Tests/Cpu/CpuTestSimd32.cs | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

(limited to 'Ryujinx.Tests/Cpu')

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd32.cs b/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
index 45c42ddf..4b068dda 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
@@ -154,6 +154,15 @@ namespace Ryujinx.Tests.Cpu
                 yield return rnd2;
             }
         }
+
+        private static IEnumerable<ulong> _GenPopCnt8B_()
+        {
+            for (ulong cnt = 0ul; cnt <= 255ul; cnt++)
+            {
+                yield return (cnt << 56) | (cnt << 48) | (cnt << 40) | (cnt << 32) |
+                             (cnt << 24) | (cnt << 16) | (cnt << 08) | cnt;
+            }
+        }
 #endregion
 
         private const int RndCnt = 2;
@@ -217,6 +226,34 @@ namespace Ryujinx.Tests.Cpu
 
             CompareAgainstUnicorn();
         }
+
+        [Test, Pairwise, Description("VCNT.8 D0, D0 | VCNT.8 Q0, Q0")]
+        public void Vcnt([Values(0u, 1u)] uint rd,
+                         [Values(0u, 1u)] uint rm,
+                         [ValueSource(nameof(_GenPopCnt8B_))] [Random(RndCnt)] ulong d0,
+                         [Values] bool q)
+        {
+            ulong d1 = ~d0; // It's expensive to have a second generator.
+
+            uint opcode = 0xf3b00500u; // VCNT.8 D0, D0
+
+            if (q)
+            {
+                opcode |= 1u << 6;
+
+                rd &= ~1u;
+                rm &= ~1u;
+            }
+
+            opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
+            opcode |= ((rm & 0xf) << 0)  | ((rm & 0x10) << 1);
+
+            V128 v0 = MakeVectorE0E1(d0, d1);
+
+            SingleOpcode(opcode, v0: v0);
+
+            CompareAgainstUnicorn();
+        }
 #endif
     }
 }
-- 
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