From 42e4e02a648812c4dee1574a5cd9e7dddf7b2458 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Sat, 1 Sep 2018 16:52:51 +0200 Subject: Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) * Update AOpCodeTable.cs * Update AInstEmitSimdCvt.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Add QCFlagBit. * Add QCFlagBit. --- Ryujinx.Tests/Cpu/Tester/Instructions.cs | 572 +++++++++++++++++++++++++++++++ 1 file changed, 572 insertions(+) (limited to 'Ryujinx.Tests/Cpu/Tester/Instructions.cs') diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs index 206d3963..e3aa4e40 100644 --- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs +++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs @@ -2685,6 +2685,154 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // fcvtns_advsimd.html#FCVTNS_asisdmisc_R + public static void Fcvtns_S(Bits sz, Bits Rn, Bits Rd) + { + const bool U = false; + const bool o2 = false; + const bool o1 = false; + + /* Decode Scalar */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + int esize = 32 << (int)UInt(sz); + int datasize = esize; + int elements = 1; + + FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); + + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand = V(datasize, n); + Bits element; + + for (int e = 0; e <= elements - 1; e++) + { + element = Elem(operand, e, esize); + + Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); + } + + V(d, result); + } + + // fcvtns_advsimd.html#FCVTNS_asimdmisc_R + public static void Fcvtns_V(bool Q, Bits sz, Bits Rn, Bits Rd) + { + const bool U = false; + const bool o2 = false; + const bool o1 = false; + + /* Decode Vector */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + /* if sz:Q == '10' then ReservedValue(); */ + + int esize = 32 << (int)UInt(sz); + int datasize = (Q ? 128 : 64); + int elements = datasize / esize; + + FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); + + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand = V(datasize, n); + Bits element; + + for (int e = 0; e <= elements - 1; e++) + { + element = Elem(operand, e, esize); + + Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); + } + + V(d, result); + } + + // fcvtnu_advsimd.html#FCVTNU_asisdmisc_R + public static void Fcvtnu_S(Bits sz, Bits Rn, Bits Rd) + { + const bool U = true; + const bool o2 = false; + const bool o1 = false; + + /* Decode Scalar */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + int esize = 32 << (int)UInt(sz); + int datasize = esize; + int elements = 1; + + FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); + + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand = V(datasize, n); + Bits element; + + for (int e = 0; e <= elements - 1; e++) + { + element = Elem(operand, e, esize); + + Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); + } + + V(d, result); + } + + // fcvtnu_advsimd.html#FCVTNU_asimdmisc_R + public static void Fcvtnu_V(bool Q, Bits sz, Bits Rn, Bits Rd) + { + const bool U = true; + const bool o2 = false; + const bool o1 = false; + + /* Decode Vector */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + /* if sz:Q == '10' then ReservedValue(); */ + + int esize = 32 << (int)UInt(sz); + int datasize = (Q ? 128 : 64); + int elements = datasize / esize; + + FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); + + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand = V(datasize, n); + Bits element; + + for (int e = 0; e <= elements - 1; e++) + { + element = Elem(operand, e, esize); + + Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); + } + + V(d, result); + } + // neg_advsimd.html#NEG_asisdmisc_R public static void Neg_S(Bits size, Bits Rn, Bits Rd) { @@ -5122,6 +5270,57 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // saddl_advsimd.html + public static void Saddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = false; + const bool o1 = false; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + BigInteger element1; + BigInteger element2; + BigInteger sum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + if (sub_op) + { + sum = element1 - element2; + } + else + { + sum = element1 + element2; + } + + Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); + } + + V(d, result); + } + // saddw_advsimd.html public static void Saddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) { @@ -5333,6 +5532,116 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // smlal_advsimd_vec.html + public static void Smlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = false; + const bool o1 = false; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + Bits operand3 = V(2 * datasize, d); + BigInteger element1; + BigInteger element2; + Bits product; + Bits accum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); + + if (sub_op) + { + accum = Elem(operand3, e, 2 * esize) - product; + } + else + { + accum = Elem(operand3, e, 2 * esize) + product; + } + + Elem(result, e, 2 * esize, accum); + } + + V(d, result); + } + + // smlsl_advsimd_vec.html + public static void Smlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = false; + const bool o1 = true; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + Bits operand3 = V(2 * datasize, d); + BigInteger element1; + BigInteger element2; + Bits product; + Bits accum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); + + if (sub_op) + { + accum = Elem(operand3, e, 2 * esize) - product; + } + else + { + accum = Elem(operand3, e, 2 * esize) + product; + } + + Elem(result, e, 2 * esize, accum); + } + + V(d, result); + } + // sqadd_advsimd.html#SQADD_asisdsame_only public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd) { @@ -5771,6 +6080,57 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // ssubl_advsimd.html + public static void Ssubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = false; + const bool o1 = true; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + BigInteger element1; + BigInteger element2; + BigInteger sum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + if (sub_op) + { + sum = element1 - element2; + } + else + { + sum = element1 + element2; + } + + Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); + } + + V(d, result); + } + // ssubw_advsimd.html public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) { @@ -6212,6 +6572,57 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // uaddl_advsimd.html + public static void Uaddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = true; + const bool o1 = false; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + BigInteger element1; + BigInteger element2; + BigInteger sum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + if (sub_op) + { + sum = element1 - element2; + } + else + { + sum = element1 + element2; + } + + Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); + } + + V(d, result); + } + // uaddw_advsimd.html public static void Uaddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) { @@ -6345,6 +6756,116 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // umlal_advsimd_vec.html + public static void Umlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = true; + const bool o1 = false; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + Bits operand3 = V(2 * datasize, d); + BigInteger element1; + BigInteger element2; + Bits product; + Bits accum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); + + if (sub_op) + { + accum = Elem(operand3, e, 2 * esize) - product; + } + else + { + accum = Elem(operand3, e, 2 * esize) + product; + } + + Elem(result, e, 2 * esize, accum); + } + + V(d, result); + } + + // umlsl_advsimd_vec.html + public static void Umlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = true; + const bool o1 = true; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + Bits operand3 = V(2 * datasize, d); + BigInteger element1; + BigInteger element2; + Bits product; + Bits accum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); + + if (sub_op) + { + accum = Elem(operand3, e, 2 * esize) - product; + } + else + { + accum = Elem(operand3, e, 2 * esize) + product; + } + + Elem(result, e, 2 * esize, accum); + } + + V(d, result); + } + // uqadd_advsimd.html#UQADD_asisdsame_only public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd) { @@ -6579,6 +7100,57 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // usubl_advsimd.html + public static void Usubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = true; + const bool o1 = true; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = 64; + int part = (int)UInt(Q); + int elements = datasize / esize; + + bool sub_op = (o1 == true); + bool unsigned = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(2 * datasize); + Bits operand1 = Vpart(datasize, n, part); + Bits operand2 = Vpart(datasize, m, part); + BigInteger element1; + BigInteger element2; + BigInteger sum; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = Int(Elem(operand1, e, esize), unsigned); + element2 = Int(Elem(operand2, e, esize), unsigned); + + if (sub_op) + { + sum = element1 - element2; + } + else + { + sum = element1 + element2; + } + + Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); + } + + V(d, result); + } + // usubw_advsimd.html public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) { -- cgit v1.2.3