From 7c111a356704bc86038d2001f9bbe56d27152590 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Thu, 14 Nov 2019 03:08:07 +0100
Subject: Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)

* Add Mrs & Msr (Nzcv) Inst., with Tests.

* Don't use `NativeInterface`.
---
 Ryujinx.Tests/Cpu/CpuTestSystem.cs | 73 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 Ryujinx.Tests/Cpu/CpuTestSystem.cs

(limited to 'Ryujinx.Tests/Cpu/CpuTestSystem.cs')

diff --git a/Ryujinx.Tests/Cpu/CpuTestSystem.cs b/Ryujinx.Tests/Cpu/CpuTestSystem.cs
new file mode 100644
index 00000000..02b1f1bd
--- /dev/null
+++ b/Ryujinx.Tests/Cpu/CpuTestSystem.cs
@@ -0,0 +1,73 @@
+#define System
+
+using ARMeilleure.State;
+
+using NUnit.Framework;
+
+using System.Collections.Generic;
+
+namespace Ryujinx.Tests.Cpu
+{
+    [Category("System")]
+    public sealed class CpuTestSystem : CpuTest
+    {
+#if System
+
+#region "ValueSource (Types)"
+        private static IEnumerable<ulong> _GenNzcv_()
+        {
+            yield return 0x0000000000000000ul;
+            yield return 0x7FFFFFFFFFFFFFFFul;
+            yield return 0x8000000000000000ul;
+            yield return 0xFFFFFFFFFFFFFFFFul;
+
+            bool v = TestContext.CurrentContext.Random.NextBool();
+            bool c = TestContext.CurrentContext.Random.NextBool();
+            bool z = TestContext.CurrentContext.Random.NextBool();
+            bool n = TestContext.CurrentContext.Random.NextBool();
+
+            ulong rnd = 0UL;
+
+            rnd |= (v ? 1UL : 0UL) << (int)PState.VFlag;
+            rnd |= (c ? 1UL : 0UL) << (int)PState.CFlag;
+            rnd |= (z ? 1UL : 0UL) << (int)PState.ZFlag;
+            rnd |= (n ? 1UL : 0UL) << (int)PState.NFlag;
+
+            yield return rnd;
+        }
+#endregion
+
+#region "ValueSource (Opcodes)"
+        private static uint[] _MrsMsr_Nzcv_()
+        {
+            return new uint[]
+            {
+                0xD53B4200u, // MRS X0, NZCV
+                0xD51B4200u  // MSR NZCV, X0
+            };
+        }
+#endregion
+
+        private const int RndCnt = 2;
+
+        [Test, Pairwise]
+        public void MrsMsr_Nzcv([ValueSource("_MrsMsr_Nzcv_")] uint opcodes,
+                                [Values(0u, 1u, 31u)] uint rt,
+                                [ValueSource("_GenNzcv_")] [Random(RndCnt)] ulong xt)
+        {
+            opcodes |= (rt & 31) << 0;
+
+            bool v = TestContext.CurrentContext.Random.NextBool();
+            bool c = TestContext.CurrentContext.Random.NextBool();
+            bool z = TestContext.CurrentContext.Random.NextBool();
+            bool n = TestContext.CurrentContext.Random.NextBool();
+
+            ulong x31 = TestContext.CurrentContext.Random.NextULong();
+
+            SingleOpcode(opcodes, x0: xt, x1: xt, x31: x31, overflow: v, carry: c, zero: z, negative: n);
+
+            CompareAgainstUnicorn();
+        }
+#endif
+    }
+}
-- 
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