From a731ab3a2aad56e6ceb8b4e2444a61353246295c Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 8 Aug 2019 15:56:22 -0300 Subject: Add a new JIT compiler for CPU code (#693) * Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary --- Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs | 69 +++++++++++++++++++------------------ 1 file changed, 35 insertions(+), 34 deletions(-) (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs') diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs b/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs index 69195af2..5e6546ab 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs @@ -1,9 +1,10 @@ #define SimdTbl +using ARMeilleure.State; + using NUnit.Framework; using System.Collections.Generic; -using System.Runtime.Intrinsics; namespace Ryujinx.Tests.Cpu { @@ -146,9 +147,9 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v0 = MakeVectorE0E1(z, z); - Vector128 v1 = MakeVectorE0E1(table0, table0); - Vector128 v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(table0, table0); + V128 v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); @@ -169,10 +170,10 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v0 = MakeVectorE0E1(z, z); - Vector128 v1 = MakeVectorE0E1(table0, table0); - Vector128 v2 = MakeVectorE0E1(table1, table1); - Vector128 v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(table0, table0); + V128 v2 = MakeVectorE0E1(table1, table1); + V128 v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3); @@ -193,10 +194,10 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v30 = MakeVectorE0E1(z, z); - Vector128 v31 = MakeVectorE0E1(table0, table0); - Vector128 v0 = MakeVectorE0E1(table1, table1); - Vector128 v1 = MakeVectorE0E1(indexes, indexes); + V128 v30 = MakeVectorE0E1(z, z); + V128 v31 = MakeVectorE0E1(table0, table0); + V128 v0 = MakeVectorE0E1(table1, table1); + V128 v1 = MakeVectorE0E1(indexes, indexes); SingleOpcode(opcodes, v0: v0, v1: v1, v30: v30, v31: v31); @@ -218,11 +219,11 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v0 = MakeVectorE0E1(z, z); - Vector128 v1 = MakeVectorE0E1(table0, table0); - Vector128 v2 = MakeVectorE0E1(table1, table1); - Vector128 v3 = MakeVectorE0E1(table2, table2); - Vector128 v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(table0, table0); + V128 v2 = MakeVectorE0E1(table1, table1); + V128 v3 = MakeVectorE0E1(table2, table2); + V128 v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4); @@ -244,11 +245,11 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v30 = MakeVectorE0E1(z, z); - Vector128 v31 = MakeVectorE0E1(table0, table0); - Vector128 v0 = MakeVectorE0E1(table1, table1); - Vector128 v1 = MakeVectorE0E1(table2, table2); - Vector128 v2 = MakeVectorE0E1(indexes, indexes); + V128 v30 = MakeVectorE0E1(z, z); + V128 v31 = MakeVectorE0E1(table0, table0); + V128 v0 = MakeVectorE0E1(table1, table1); + V128 v1 = MakeVectorE0E1(table2, table2); + V128 v2 = MakeVectorE0E1(indexes, indexes); SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v30: v30, v31: v31); @@ -271,12 +272,12 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v0 = MakeVectorE0E1(z, z); - Vector128 v1 = MakeVectorE0E1(table0, table0); - Vector128 v2 = MakeVectorE0E1(table1, table1); - Vector128 v3 = MakeVectorE0E1(table2, table2); - Vector128 v4 = MakeVectorE0E1(table3, table3); - Vector128 v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(table0, table0); + V128 v2 = MakeVectorE0E1(table1, table1); + V128 v3 = MakeVectorE0E1(table2, table2); + V128 v4 = MakeVectorE0E1(table3, table3); + V128 v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul); SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5); @@ -299,12 +300,12 @@ namespace Ryujinx.Tests.Cpu opcodes |= ((q & 1) << 30); ulong z = TestContext.CurrentContext.Random.NextULong(); - Vector128 v30 = MakeVectorE0E1(z, z); - Vector128 v31 = MakeVectorE0E1(table0, table0); - Vector128 v0 = MakeVectorE0E1(table1, table1); - Vector128 v1 = MakeVectorE0E1(table2, table2); - Vector128 v2 = MakeVectorE0E1(table3, table3); - Vector128 v3 = MakeVectorE0E1(indexes, indexes); + V128 v30 = MakeVectorE0E1(z, z); + V128 v31 = MakeVectorE0E1(table0, table0); + V128 v0 = MakeVectorE0E1(table1, table1); + V128 v1 = MakeVectorE0E1(table2, table2); + V128 v2 = MakeVectorE0E1(table3, table3); + V128 v3 = MakeVectorE0E1(indexes, indexes); SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v30: v30, v31: v31); -- cgit v1.2.3