From 0f5b6dfbe8d4bcc4df3f670e366a967d8ea103db Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Wed, 26 Dec 2018 18:11:36 +0100
Subject: Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. &
 SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V,
 Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for
 Xtn_V Inst.. Add Tests. (#543)

* Update Optimizations.cs

* Update InstEmitSimdShift.cs

* Update InstEmitSimdHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdMove.cs

* Update SoftFloat.cs

* Update InstEmitSimdCmp.cs

* Update CpuTestSimdShImm.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFloat.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update CpuTestSimd.cs

* Explicit some implicit casts.

* Simplify some powers; nits.

* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update CpuTestSimdReg.cs

* Update InstEmitSimdArithmetic.cs
---
 Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs | 96 +++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

(limited to 'Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs')

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
index c9c4c1ed..f026158c 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
@@ -50,6 +50,33 @@ namespace Ryujinx.Tests.Cpu
 #endregion
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _SU_Shll_V_8B8H_16B8H_()
+        {
+            return new uint[]
+            {
+                0x0F08A400u, // SSHLL V0.8H, V0.8B, #0
+                0x2F08A400u  // USHLL V0.8H, V0.8B, #0
+            };
+        }
+
+        private static uint[] _SU_Shll_V_4H4S_8H4S_()
+        {
+            return new uint[]
+            {
+                0x0F10A400u, // SSHLL V0.4S, V0.4H, #0
+                0x2F10A400u  // USHLL V0.4S, V0.4H, #0
+            };
+        }
+
+        private static uint[] _SU_Shll_V_2S2D_4S2D_()
+        {
+            return new uint[]
+            {
+                0x0F20A400u, // SSHLL V0.2D, V0.2S, #0
+                0x2F20A400u  // USHLL V0.2D, V0.2S, #0
+            };
+        }
+
         private static uint[] _ShrImm_S_D_()
         {
             return new uint[]
@@ -344,6 +371,75 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
+        [Test, Pairwise]
+        public void SU_Shll_V_8B8H_16B8H([ValueSource("_SU_Shll_V_8B8H_16B8H_")] uint opcodes,
+                                         [Values(0u)]     uint rd,
+                                         [Values(1u, 0u)] uint rn,
+                                         [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
+                                         [ValueSource("_8B_")] [Random(RndCnt)] ulong a,
+                                         [Range(0u, 7u)] uint shift,
+                                         [Values(0b0u, 0b1u)] uint q) // <8B8H, 16B8H>
+        {
+            uint immHb = (8 + shift) & 0x7F;
+
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= (immHb << 16);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void SU_Shll_V_4H4S_8H4S([ValueSource("_SU_Shll_V_4H4S_8H4S_")] uint opcodes,
+                                        [Values(0u)]     uint rd,
+                                        [Values(1u, 0u)] uint rn,
+                                        [ValueSource("_4H_")] [Random(RndCnt)] ulong z,
+                                        [ValueSource("_4H_")] [Random(RndCnt)] ulong a,
+                                        [Range(0u, 15u)] uint shift,
+                                        [Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
+        {
+            uint immHb = (16 + shift) & 0x7F;
+
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= (immHb << 16);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void SU_Shll_V_2S2D_4S2D([ValueSource("_SU_Shll_V_2S2D_4S2D_")] uint opcodes,
+                                        [Values(0u)]     uint rd,
+                                        [Values(1u, 0u)] uint rn,
+                                        [ValueSource("_2S_")] [Random(RndCnt)] ulong z,
+                                        [ValueSource("_2S_")] [Random(RndCnt)] ulong a,
+                                        [Range(0u, 31u)] uint shift,
+                                        [Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
+        {
+            uint immHb = (32 + shift) & 0x7F;
+
+            opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcodes |= (immHb << 16);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
         [Test, Pairwise]
         public void ShrImm_S_D([ValueSource("_ShrImm_S_D_")] uint opcodes,
                                [Values(0u)]     uint rd,
-- 
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