From 3af2ce74ecf76cc8d6fdb9ff19101bfee47af7dd Mon Sep 17 00:00:00 2001 From: Valentin PONS Date: Sun, 19 Jul 2020 14:11:58 -0400 Subject: Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) * Added some 32 bits instructions: * VBIC * VTST * VSRA * Incremented the PTC * Add tests and fix implementation * Fixed VBIC immediate opcode mapping * Hey hey! * Nit. Co-authored-by: gdkchan Co-authored-by: LDj3SNuD Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> --- Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs') diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index dbe69124..866f50a9 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -28,7 +28,7 @@ namespace Ryujinx.Tests.Cpu { 0xf3000d00u, // VPADD.F32 D0, D0, D0 0xf3000f00u, // VPMAX.F32 D0, D0, D0 - 0xf3200f00u // VPMIN.F32 D0, D0, D0 + 0xf3200f00u // VPMIN.F32 D0, D0, D0 }; } @@ -41,7 +41,7 @@ namespace Ryujinx.Tests.Cpu { VpaddI8, 0xf2000a00u, // VPMAX.S8 D0, D0, D0 - 0xf2000a10u // VPMIN.S8 D0, D0, D0 + 0xf2000a10u // VPMIN.S8 D0, D0, D0 }; } #endregion @@ -189,7 +189,7 @@ namespace Ryujinx.Tests.Cpu [Explicit] [Test, Pairwise, Description("VADD.f32 V0, V0, V0")] - public void Vadd_f32([Values(0u)] uint rd, + public void Vadd_f32([Values(0u)] uint rd, [Values(0u, 1u)] uint rn, [Values(0u, 2u)] uint rm, [ValueSource("_2S_F_")] ulong z0, -- cgit v1.2.3