From db45688aa8d0e63d3ffbe50351722ef32f8360f8 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Fri, 9 Sep 2022 21:47:38 -0300
Subject: Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB,
 VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)

* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions

* PPTC version

* Fix VQADD/VQSUB

* Improve MRC/MCR handling and exception messages

In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
---
 Ryujinx.Tests/Cpu/CpuTestSimd32.cs | 93 ++++++++++++++++++++++++++------------
 1 file changed, 65 insertions(+), 28 deletions(-)

(limited to 'Ryujinx.Tests/Cpu/CpuTestSimd32.cs')

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd32.cs b/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
index 34e94068..34173cd7 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
@@ -12,12 +12,22 @@ namespace Ryujinx.Tests.Cpu
 #if Simd32
 
 #region "ValueSource (Opcodes)"
-        private static uint[] _Vabs_Vneg_V_()
+        private static uint[] _Vabs_Vneg_Vpaddl_I_()
         {
             return new uint[]
             {
-                0xf3b10300u, // VABS.S8 D0, D0
-                0xf3b10380u  // VNEG.S8 D0, D0
+                0xf3b10300u, // VABS.S8   D0, D0
+                0xf3b10380u, // VNEG.S8   D0, D0
+                0xf3b00200u  // VPADDL.S8 D0, D0
+            };
+        }
+
+        private static uint[] _Vabs_Vneg_F_()
+        {
+            return new uint[]
+            {
+                0xf3b90700u, // VABS.F32 D0, D0
+                0xf3b90780u  // VNEG.F32 D0, D0
             };
         }
 #endregion
@@ -201,40 +211,43 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise]
-        public void Vabs_Vneg_V_S8_S16_S32([ValueSource("_Vabs_Vneg_V_")] uint opcode,
-                                           [Range(0u, 3u)] uint rd,
-                                           [Range(0u, 3u)] uint rm,
-                                           [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
-                                           [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
-                                           [Values(0u, 1u, 2u)] uint size, // <S8, S16, S32>
-                                           [Values] bool q)
+        public void Vabs_Vneg_Vpaddl_V_I([ValueSource("_Vabs_Vneg_Vpaddl_I_")] uint opcode,
+                                         [Range(0u, 3u)] uint rd,
+                                         [Range(0u, 3u)] uint rm,
+                                         [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
+                                         [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
+                                         [Values(0u, 1u, 2u)] uint size, // <S8, S16, S32>
+                                         [Values] bool q)
         {
-            const bool f = false;
+            if (q)
+            {
+                opcode |= 1 << 6;
+
+                rd >>= 1; rd <<= 1;
+                rm >>= 1; rm <<= 1;
+            }
 
-            Vabs_Vneg_V(opcode, rd, rm, z, b, size, f, q);
+            opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
+            opcode |= ((rm & 0xf) << 0)  | ((rm & 0x10) << 1);
+
+            opcode |= (size & 0x3) << 18;
+
+            V128 v0 = MakeVectorE0E1(z, ~z);
+            V128 v1 = MakeVectorE0E1(b, ~b);
+
+            SingleOpcode(opcode, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
         }
 
         [Test, Pairwise]
-        public void Vabs_Vneg_V_F32([ValueSource("_Vabs_Vneg_V_")] uint opcode,
+        public void Vabs_Vneg_V_F32([ValueSource("_Vabs_Vneg_F_")] uint opcode,
                                     [Range(0u, 3u)] uint rd,
                                     [Range(0u, 3u)] uint rm,
                                     [ValueSource("_2S_F_")] ulong z,
                                     [ValueSource("_2S_F_")] ulong b,
                                     [Values] bool q)
         {
-            const uint size = 0b10; // <F32>
-            const bool f = true;
-
-            Vabs_Vneg_V(opcode, rd, rm, z, b, size, f, q);
-        }
-
-        private void Vabs_Vneg_V(uint opcode, uint rd, uint rm, ulong z, ulong b, uint size, bool f, bool q)
-        {
-            if (f)
-            {
-                opcode |= 1 << 10;
-            }
-
             if (q)
             {
                 opcode |= 1 << 6;
@@ -246,8 +259,6 @@ namespace Ryujinx.Tests.Cpu
             opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
             opcode |= ((rm & 0xf) << 0)  | ((rm & 0x10) << 1);
 
-            opcode |= (size & 0x3) << 18;
-
             V128 v0 = MakeVectorE0E1(z, ~z);
             V128 v1 = MakeVectorE0E1(b, ~b);
 
@@ -283,6 +294,32 @@ namespace Ryujinx.Tests.Cpu
 
             CompareAgainstUnicorn();
         }
+
+        [Test, Pairwise]
+        public void Vmovn_V([Range(0u, 3u)] uint rd,
+                            [Range(0u, 3u)] uint rm,
+                            [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
+                            [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
+                            [Values(0u, 1u, 2u, 3u)] uint op,
+                            [Values(0u, 1u, 2u)] uint size) // <S8, S16, S32>
+        {
+            rm >>= 1; rm <<= 1;
+
+            uint opcode = 0xf3b20200u; // VMOVN.S16 D0, Q0
+
+            opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
+            opcode |= ((rm & 0xf) << 0)  | ((rm & 0x10) << 1);
+
+            opcode |= (op & 0x3) << 6;
+            opcode |= (size & 0x3) << 18;
+
+            V128 v0 = MakeVectorE0E1(z, ~z);
+            V128 v1 = MakeVectorE0E1(b, ~b);
+
+            SingleOpcode(opcode, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
 #endif
     }
 }
-- 
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