From e21ebbf666f10d39d44a0856e5a44143d3d69d0d Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Wed, 27 Feb 2019 23:03:31 -0300
Subject: Misc. CPU optimizations (#575)

* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0

* Refactoring

* Add a config entry to enable or disable the reg load/store opt.

* Remove unnecessary register state stores for calls when the callee is know

* Rename IoType to VarType

* Enable tier 0 while fixing some perf issues related to tier 0

* Small tweak -- Compile before adding to the cache, to avoid lags

* Add required config entry
---
 ChocolArm64/Translation/ILOpCodeLoadField.cs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'ChocolArm64/Translation/ILOpCodeLoadField.cs')

diff --git a/ChocolArm64/Translation/ILOpCodeLoadField.cs b/ChocolArm64/Translation/ILOpCodeLoadField.cs
index abcd37c3..f0507ac2 100644
--- a/ChocolArm64/Translation/ILOpCodeLoadField.cs
+++ b/ChocolArm64/Translation/ILOpCodeLoadField.cs
@@ -5,7 +5,7 @@ namespace ChocolArm64.Translation
 {
     struct ILOpCodeLoadField : IILEmit
     {
-        public FieldInfo Info { get; private set; }
+        public FieldInfo Info { get; }
 
         public ILOpCodeLoadField(FieldInfo info)
         {
-- 
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