From e21ebbf666f10d39d44a0856e5a44143d3d69d0d Mon Sep 17 00:00:00 2001 From: gdkchan Date: Wed, 27 Feb 2019 23:03:31 -0300 Subject: Misc. CPU optimizations (#575) * Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry --- ChocolArm64/Translation/ILOpCodeCall.cs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ChocolArm64/Translation/ILOpCodeCall.cs') diff --git a/ChocolArm64/Translation/ILOpCodeCall.cs b/ChocolArm64/Translation/ILOpCodeCall.cs index c046aeeb..dc20417a 100644 --- a/ChocolArm64/Translation/ILOpCodeCall.cs +++ b/ChocolArm64/Translation/ILOpCodeCall.cs @@ -5,9 +5,9 @@ namespace ChocolArm64.Translation { struct ILOpCodeCall : IILEmit { - public MethodInfo Info { get; private set; } + public MethodInfo Info { get; } - public bool IsVirtual { get; private set; } + public bool IsVirtual { get; } public ILOpCodeCall(MethodInfo info, bool isVirtual) { -- cgit v1.2.3