From a694420d11ef74e4f0bf473be2b6f64635bc89c7 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Mon, 4 Feb 2019 18:26:05 -0300
Subject: Implement speculative translation on the CPU (#515)

* Implement speculative translation on the cpu, and change the way how branches to unknown or untranslated addresses works

* Port t0opt changes and other cleanups

* Change namespace from translation related classes to ChocolArm64.Translation, other minor tweaks

* Fix typo

* Translate higher quality code for indirect jumps aswell, and on some cases that were missed when lower quality (tier 0) code was available

* Remove debug print

* Remove direct argument passing optimization, and enable tail calls for BR instructions

* Call delegates directly with Callvirt rather than calling Execute, do not emit calls for tier 0 code

* Remove unused property

* Rename argument on ArmSubroutine delegate
---
 ChocolArm64/Translation/ILMethodBuilder.cs | 54 ++++--------------------------
 1 file changed, 6 insertions(+), 48 deletions(-)

(limited to 'ChocolArm64/Translation/ILMethodBuilder.cs')

diff --git a/ChocolArm64/Translation/ILMethodBuilder.cs b/ChocolArm64/Translation/ILMethodBuilder.cs
index 70d9a2db..892f831b 100644
--- a/ChocolArm64/Translation/ILMethodBuilder.cs
+++ b/ChocolArm64/Translation/ILMethodBuilder.cs
@@ -26,72 +26,30 @@ namespace ChocolArm64.Translation
             _subName  = subName;
         }
 
-        public TranslatedSub GetSubroutine()
+        public TranslatedSub GetSubroutine(TranslationTier tier)
         {
             LocalAlloc = new LocalAlloc(_ilBlocks, _ilBlocks[0]);
 
-            List<Register> subArgs = new List<Register>();
-
-            void SetArgs(long inputs, RegisterType baseType)
-            {
-                for (int bit = 0; bit < 64; bit++)
-                {
-                    long mask = 1L << bit;
-
-                    if ((inputs & mask) != 0)
-                    {
-                        subArgs.Add(GetRegFromBit(bit, baseType));
-                    }
-                }
-            }
-
-            SetArgs(LocalAlloc.GetIntInputs(_ilBlocks[0]), RegisterType.Int);
-            SetArgs(LocalAlloc.GetVecInputs(_ilBlocks[0]), RegisterType.Vector);
-
-            DynamicMethod method = new DynamicMethod(_subName, typeof(long), GetArgumentTypes(subArgs));
+            DynamicMethod method = new DynamicMethod(_subName, typeof(long), TranslatedSub.FixedArgTypes);
 
             Generator = method.GetILGenerator();
 
-            TranslatedSub subroutine = new TranslatedSub(method, subArgs);
-
-            int argsStart = TranslatedSub.FixedArgTypes.Length;
+            TranslatedSub subroutine = new TranslatedSub(method, tier);
 
             _locals = new Dictionary<Register, int>();
 
             _localsCount = 0;
 
-            for (int index = 0; index < subroutine.SubArgs.Count; index++)
-            {
-                Register reg = subroutine.SubArgs[index];
-
-                Generator.EmitLdarg(index + argsStart);
-                Generator.EmitStloc(GetLocalIndex(reg));
-            }
+            new ILOpCodeLoadState(_ilBlocks[0]).Emit(this);
 
             foreach (ILBlock ilBlock in _ilBlocks)
             {
                 ilBlock.Emit(this);
             }
 
-            return subroutine;
-        }
-
-        private Type[] GetArgumentTypes(IList<Register> Params)
-        {
-            Type[] fixedArgs = TranslatedSub.FixedArgTypes;
-
-            Type[] output = new Type[Params.Count + fixedArgs.Length];
-
-            fixedArgs.CopyTo(output, 0);
+            subroutine.PrepareMethod();
 
-            int typeIdx = fixedArgs.Length;
-
-            for (int index = 0; index < Params.Count; index++)
-            {
-                output[typeIdx++] = GetFieldType(Params[index].Type);
-            }
-
-            return output;
+            return subroutine;
         }
 
         public int GetLocalIndex(Register reg)
-- 
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