From 9cb57fb4bb3bbae0ae052a5af4a96a49fc5d864d Mon Sep 17 00:00:00 2001 From: Alex Barney Date: Tue, 30 Oct 2018 19:43:02 -0600 Subject: Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) * Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment --- ChocolArm64/State/AExecutionMode.cs | 8 -- ChocolArm64/State/APState.cs | 23 ----- ChocolArm64/State/ARegister.cs | 142 ------------------------------- ChocolArm64/State/ARegisterSize.cs | 10 --- ChocolArm64/State/ARegisterType.cs | 9 -- ChocolArm64/State/ARoundMode.cs | 10 --- ChocolArm64/State/AThreadState.cs | 164 ------------------------------------ ChocolArm64/State/CpuThreadState.cs | 164 ++++++++++++++++++++++++++++++++++++ ChocolArm64/State/ExecutionMode.cs | 8 ++ ChocolArm64/State/FPCR.cs | 11 --- ChocolArm64/State/FPExc.cs | 12 --- ChocolArm64/State/FPSR.cs | 8 -- ChocolArm64/State/FPType.cs | 11 --- ChocolArm64/State/FpExc.cs | 12 +++ ChocolArm64/State/FpType.cs | 11 +++ ChocolArm64/State/Fpcr.cs | 11 +++ ChocolArm64/State/Fpsr.cs | 8 ++ ChocolArm64/State/PState.cs | 23 +++++ ChocolArm64/State/Register.cs | 142 +++++++++++++++++++++++++++++++ ChocolArm64/State/RegisterSize.cs | 10 +++ ChocolArm64/State/RegisterType.cs | 9 ++ ChocolArm64/State/RoundMode.cs | 10 +++ 22 files changed, 408 insertions(+), 408 deletions(-) delete mode 100644 ChocolArm64/State/AExecutionMode.cs delete mode 100644 ChocolArm64/State/APState.cs delete mode 100644 ChocolArm64/State/ARegister.cs delete mode 100644 ChocolArm64/State/ARegisterSize.cs delete mode 100644 ChocolArm64/State/ARegisterType.cs delete mode 100644 ChocolArm64/State/ARoundMode.cs delete mode 100644 ChocolArm64/State/AThreadState.cs create mode 100644 ChocolArm64/State/CpuThreadState.cs create mode 100644 ChocolArm64/State/ExecutionMode.cs delete mode 100644 ChocolArm64/State/FPCR.cs delete mode 100644 ChocolArm64/State/FPExc.cs delete mode 100644 ChocolArm64/State/FPSR.cs delete mode 100644 ChocolArm64/State/FPType.cs create mode 100644 ChocolArm64/State/FpExc.cs create mode 100644 ChocolArm64/State/FpType.cs create mode 100644 ChocolArm64/State/Fpcr.cs create mode 100644 ChocolArm64/State/Fpsr.cs create mode 100644 ChocolArm64/State/PState.cs create mode 100644 ChocolArm64/State/Register.cs create mode 100644 ChocolArm64/State/RegisterSize.cs create mode 100644 ChocolArm64/State/RegisterType.cs create mode 100644 ChocolArm64/State/RoundMode.cs (limited to 'ChocolArm64/State') diff --git a/ChocolArm64/State/AExecutionMode.cs b/ChocolArm64/State/AExecutionMode.cs deleted file mode 100644 index 8632da77..00000000 --- a/ChocolArm64/State/AExecutionMode.cs +++ /dev/null @@ -1,8 +0,0 @@ -namespace ChocolArm64.State -{ - enum AExecutionMode - { - AArch32, - AArch64 - } -} \ No newline at end of file diff --git a/ChocolArm64/State/APState.cs b/ChocolArm64/State/APState.cs deleted file mode 100644 index aaf0ff0c..00000000 --- a/ChocolArm64/State/APState.cs +++ /dev/null @@ -1,23 +0,0 @@ -using System; - -namespace ChocolArm64.State -{ - [Flags] - enum APState - { - VBit = 28, - CBit = 29, - ZBit = 30, - NBit = 31, - - V = 1 << VBit, - C = 1 << CBit, - Z = 1 << ZBit, - N = 1 << NBit, - - NZ = N | Z, - CV = C | V, - - NZCV = NZ | CV - } -} diff --git a/ChocolArm64/State/ARegister.cs b/ChocolArm64/State/ARegister.cs deleted file mode 100644 index 5861db8c..00000000 --- a/ChocolArm64/State/ARegister.cs +++ /dev/null @@ -1,142 +0,0 @@ -using System; -using System.Reflection; - -namespace ChocolArm64.State -{ - struct ARegister - { - public int Index; - - public ARegisterType Type; - - public ARegister(int Index, ARegisterType Type) - { - this.Index = Index; - this.Type = Type; - } - - public override int GetHashCode() - { - return (ushort)Index | ((ushort)Type << 16); - } - - public override bool Equals(object Obj) - { - return Obj is ARegister Reg && - Reg.Index == Index && - Reg.Type == Type; - } - - public FieldInfo GetField() - { - switch (Type) - { - case ARegisterType.Flag: return GetFieldFlag(); - case ARegisterType.Int: return GetFieldInt(); - case ARegisterType.Vector: return GetFieldVector(); - } - - throw new InvalidOperationException(); - } - - private FieldInfo GetFieldFlag() - { - switch ((APState)Index) - { - case APState.VBit: return GetField(nameof(AThreadState.Overflow)); - case APState.CBit: return GetField(nameof(AThreadState.Carry)); - case APState.ZBit: return GetField(nameof(AThreadState.Zero)); - case APState.NBit: return GetField(nameof(AThreadState.Negative)); - } - - throw new InvalidOperationException(); - } - - private FieldInfo GetFieldInt() - { - switch (Index) - { - case 0: return GetField(nameof(AThreadState.X0)); - case 1: return GetField(nameof(AThreadState.X1)); - case 2: return GetField(nameof(AThreadState.X2)); - case 3: return GetField(nameof(AThreadState.X3)); - case 4: return GetField(nameof(AThreadState.X4)); - case 5: return GetField(nameof(AThreadState.X5)); - case 6: return GetField(nameof(AThreadState.X6)); - case 7: return GetField(nameof(AThreadState.X7)); - case 8: return GetField(nameof(AThreadState.X8)); - case 9: return GetField(nameof(AThreadState.X9)); - case 10: return GetField(nameof(AThreadState.X10)); - case 11: return GetField(nameof(AThreadState.X11)); - case 12: return GetField(nameof(AThreadState.X12)); - case 13: return GetField(nameof(AThreadState.X13)); - case 14: return GetField(nameof(AThreadState.X14)); - case 15: return GetField(nameof(AThreadState.X15)); - case 16: return GetField(nameof(AThreadState.X16)); - case 17: return GetField(nameof(AThreadState.X17)); - case 18: return GetField(nameof(AThreadState.X18)); - case 19: return GetField(nameof(AThreadState.X19)); - case 20: return GetField(nameof(AThreadState.X20)); - case 21: return GetField(nameof(AThreadState.X21)); - case 22: return GetField(nameof(AThreadState.X22)); - case 23: return GetField(nameof(AThreadState.X23)); - case 24: return GetField(nameof(AThreadState.X24)); - case 25: return GetField(nameof(AThreadState.X25)); - case 26: return GetField(nameof(AThreadState.X26)); - case 27: return GetField(nameof(AThreadState.X27)); - case 28: return GetField(nameof(AThreadState.X28)); - case 29: return GetField(nameof(AThreadState.X29)); - case 30: return GetField(nameof(AThreadState.X30)); - case 31: return GetField(nameof(AThreadState.X31)); - } - - throw new InvalidOperationException(); - } - - private FieldInfo GetFieldVector() - { - switch (Index) - { - case 0: return GetField(nameof(AThreadState.V0)); - case 1: return GetField(nameof(AThreadState.V1)); - case 2: return GetField(nameof(AThreadState.V2)); - case 3: return GetField(nameof(AThreadState.V3)); - case 4: return GetField(nameof(AThreadState.V4)); - case 5: return GetField(nameof(AThreadState.V5)); - case 6: return GetField(nameof(AThreadState.V6)); - case 7: return GetField(nameof(AThreadState.V7)); - case 8: return GetField(nameof(AThreadState.V8)); - case 9: return GetField(nameof(AThreadState.V9)); - case 10: return GetField(nameof(AThreadState.V10)); - case 11: return GetField(nameof(AThreadState.V11)); - case 12: return GetField(nameof(AThreadState.V12)); - case 13: return GetField(nameof(AThreadState.V13)); - case 14: return GetField(nameof(AThreadState.V14)); - case 15: return GetField(nameof(AThreadState.V15)); - case 16: return GetField(nameof(AThreadState.V16)); - case 17: return GetField(nameof(AThreadState.V17)); - case 18: return GetField(nameof(AThreadState.V18)); - case 19: return GetField(nameof(AThreadState.V19)); - case 20: return GetField(nameof(AThreadState.V20)); - case 21: return GetField(nameof(AThreadState.V21)); - case 22: return GetField(nameof(AThreadState.V22)); - case 23: return GetField(nameof(AThreadState.V23)); - case 24: return GetField(nameof(AThreadState.V24)); - case 25: return GetField(nameof(AThreadState.V25)); - case 26: return GetField(nameof(AThreadState.V26)); - case 27: return GetField(nameof(AThreadState.V27)); - case 28: return GetField(nameof(AThreadState.V28)); - case 29: return GetField(nameof(AThreadState.V29)); - case 30: return GetField(nameof(AThreadState.V30)); - case 31: return GetField(nameof(AThreadState.V31)); - } - - throw new InvalidOperationException(); - } - - private FieldInfo GetField(string Name) - { - return typeof(AThreadState).GetField(Name); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/State/ARegisterSize.cs b/ChocolArm64/State/ARegisterSize.cs deleted file mode 100644 index 144f36b9..00000000 --- a/ChocolArm64/State/ARegisterSize.cs +++ /dev/null @@ -1,10 +0,0 @@ -namespace ChocolArm64.State -{ - enum ARegisterSize - { - Int32, - Int64, - SIMD64, - SIMD128 - } -} \ No newline at end of file diff --git a/ChocolArm64/State/ARegisterType.cs b/ChocolArm64/State/ARegisterType.cs deleted file mode 100644 index f9776bb7..00000000 --- a/ChocolArm64/State/ARegisterType.cs +++ /dev/null @@ -1,9 +0,0 @@ -namespace ChocolArm64.State -{ - enum ARegisterType - { - Flag, - Int, - Vector - } -} \ No newline at end of file diff --git a/ChocolArm64/State/ARoundMode.cs b/ChocolArm64/State/ARoundMode.cs deleted file mode 100644 index 297d0137..00000000 --- a/ChocolArm64/State/ARoundMode.cs +++ /dev/null @@ -1,10 +0,0 @@ -namespace ChocolArm64.State -{ - enum ARoundMode - { - ToNearest = 0, - TowardsPlusInfinity = 1, - TowardsMinusInfinity = 2, - TowardsZero = 3 - } -} diff --git a/ChocolArm64/State/AThreadState.cs b/ChocolArm64/State/AThreadState.cs deleted file mode 100644 index fbfac5bc..00000000 --- a/ChocolArm64/State/AThreadState.cs +++ /dev/null @@ -1,164 +0,0 @@ -using ChocolArm64.Events; -using System; -using System.Diagnostics; -using System.Runtime.CompilerServices; -using System.Runtime.Intrinsics; - -namespace ChocolArm64.State -{ - public class AThreadState - { - internal const int LRIndex = 30; - internal const int ZRIndex = 31; - - internal const int ErgSizeLog2 = 4; - internal const int DczSizeLog2 = 4; - - private const int MinInstForCheck = 4000000; - - internal AExecutionMode ExecutionMode; - - //AArch32 state. - public uint R0, R1, R2, R3, - R4, R5, R6, R7, - R8, R9, R10, R11, - R12, R13, R14, R15; - - public bool Thumb; - - //AArch64 state. - public ulong X0, X1, X2, X3, X4, X5, X6, X7, - X8, X9, X10, X11, X12, X13, X14, X15, - X16, X17, X18, X19, X20, X21, X22, X23, - X24, X25, X26, X27, X28, X29, X30, X31; - - public Vector128 V0, V1, V2, V3, V4, V5, V6, V7, - V8, V9, V10, V11, V12, V13, V14, V15, - V16, V17, V18, V19, V20, V21, V22, V23, - V24, V25, V26, V27, V28, V29, V30, V31; - - public bool Overflow; - public bool Carry; - public bool Zero; - public bool Negative; - - public bool Running { get; set; } - public int Core { get; set; } - - private bool Interrupted; - - private int SyncCount; - - public long TpidrEl0 { get; set; } - public long Tpidr { get; set; } - - public int Fpcr { get; set; } - public int Fpsr { get; set; } - - public int Psr - { - get - { - return (Negative ? (int)APState.N : 0) | - (Zero ? (int)APState.Z : 0) | - (Carry ? (int)APState.C : 0) | - (Overflow ? (int)APState.V : 0); - } - } - - public uint CtrEl0 => 0x8444c004; - public uint DczidEl0 => 0x00000004; - - public ulong CntfrqEl0 { get; set; } - public ulong CntpctEl0 - { - get - { - double Ticks = TickCounter.ElapsedTicks * HostTickFreq; - - return (ulong)(Ticks * CntfrqEl0); - } - } - - public event EventHandler Interrupt; - public event EventHandler Break; - public event EventHandler SvcCall; - public event EventHandler Undefined; - - private static Stopwatch TickCounter; - - private static double HostTickFreq; - - static AThreadState() - { - HostTickFreq = 1.0 / Stopwatch.Frequency; - - TickCounter = new Stopwatch(); - - TickCounter.Start(); - } - - [MethodImpl(MethodImplOptions.AggressiveInlining)] - internal bool Synchronize(int BbWeight) - { - //Firing a interrupt frequently is expensive, so we only - //do it after a given number of instructions has executed. - SyncCount += BbWeight; - - if (SyncCount >= MinInstForCheck) - { - CheckInterrupt(); - } - - return Running; - } - - internal void RequestInterrupt() - { - Interrupted = true; - } - - [MethodImpl(MethodImplOptions.NoInlining)] - private void CheckInterrupt() - { - SyncCount = 0; - - if (Interrupted) - { - Interrupted = false; - - Interrupt?.Invoke(this, EventArgs.Empty); - } - } - - internal void OnBreak(long Position, int Imm) - { - Break?.Invoke(this, new AInstExceptionEventArgs(Position, Imm)); - } - - internal void OnSvcCall(long Position, int Imm) - { - SvcCall?.Invoke(this, new AInstExceptionEventArgs(Position, Imm)); - } - - internal void OnUndefined(long Position, int RawOpCode) - { - Undefined?.Invoke(this, new AInstUndefinedEventArgs(Position, RawOpCode)); - } - - internal bool GetFpcrFlag(FPCR Flag) - { - return (Fpcr & (1 << (int)Flag)) != 0; - } - - internal void SetFpsrFlag(FPSR Flag) - { - Fpsr |= 1 << (int)Flag; - } - - internal ARoundMode FPRoundingMode() - { - return (ARoundMode)((Fpcr >> (int)FPCR.RMode) & 3); - } - } -} diff --git a/ChocolArm64/State/CpuThreadState.cs b/ChocolArm64/State/CpuThreadState.cs new file mode 100644 index 00000000..ed106f71 --- /dev/null +++ b/ChocolArm64/State/CpuThreadState.cs @@ -0,0 +1,164 @@ +using ChocolArm64.Events; +using System; +using System.Diagnostics; +using System.Runtime.CompilerServices; +using System.Runtime.Intrinsics; + +namespace ChocolArm64.State +{ + public class CpuThreadState + { + internal const int LrIndex = 30; + internal const int ZrIndex = 31; + + internal const int ErgSizeLog2 = 4; + internal const int DczSizeLog2 = 4; + + private const int MinInstForCheck = 4000000; + + internal ExecutionMode ExecutionMode; + + //AArch32 state. + public uint R0, R1, R2, R3, + R4, R5, R6, R7, + R8, R9, R10, R11, + R12, R13, R14, R15; + + public bool Thumb; + + //AArch64 state. + public ulong X0, X1, X2, X3, X4, X5, X6, X7, + X8, X9, X10, X11, X12, X13, X14, X15, + X16, X17, X18, X19, X20, X21, X22, X23, + X24, X25, X26, X27, X28, X29, X30, X31; + + public Vector128 V0, V1, V2, V3, V4, V5, V6, V7, + V8, V9, V10, V11, V12, V13, V14, V15, + V16, V17, V18, V19, V20, V21, V22, V23, + V24, V25, V26, V27, V28, V29, V30, V31; + + public bool Overflow; + public bool Carry; + public bool Zero; + public bool Negative; + + public bool Running { get; set; } + public int Core { get; set; } + + private bool _interrupted; + + private int _syncCount; + + public long TpidrEl0 { get; set; } + public long Tpidr { get; set; } + + public int Fpcr { get; set; } + public int Fpsr { get; set; } + + public int Psr + { + get + { + return (Negative ? (int)PState.N : 0) | + (Zero ? (int)PState.Z : 0) | + (Carry ? (int)PState.C : 0) | + (Overflow ? (int)PState.V : 0); + } + } + + public uint CtrEl0 => 0x8444c004; + public uint DczidEl0 => 0x00000004; + + public ulong CntfrqEl0 { get; set; } + public ulong CntpctEl0 + { + get + { + double ticks = _tickCounter.ElapsedTicks * _hostTickFreq; + + return (ulong)(ticks * CntfrqEl0); + } + } + + public event EventHandler Interrupt; + public event EventHandler Break; + public event EventHandler SvcCall; + public event EventHandler Undefined; + + private static Stopwatch _tickCounter; + + private static double _hostTickFreq; + + static CpuThreadState() + { + _hostTickFreq = 1.0 / Stopwatch.Frequency; + + _tickCounter = new Stopwatch(); + + _tickCounter.Start(); + } + + [MethodImpl(MethodImplOptions.AggressiveInlining)] + internal bool Synchronize(int bbWeight) + { + //Firing a interrupt frequently is expensive, so we only + //do it after a given number of instructions has executed. + _syncCount += bbWeight; + + if (_syncCount >= MinInstForCheck) + { + CheckInterrupt(); + } + + return Running; + } + + internal void RequestInterrupt() + { + _interrupted = true; + } + + [MethodImpl(MethodImplOptions.NoInlining)] + private void CheckInterrupt() + { + _syncCount = 0; + + if (_interrupted) + { + _interrupted = false; + + Interrupt?.Invoke(this, EventArgs.Empty); + } + } + + internal void OnBreak(long position, int imm) + { + Break?.Invoke(this, new InstExceptionEventArgs(position, imm)); + } + + internal void OnSvcCall(long position, int imm) + { + SvcCall?.Invoke(this, new InstExceptionEventArgs(position, imm)); + } + + internal void OnUndefined(long position, int rawOpCode) + { + Undefined?.Invoke(this, new InstUndefinedEventArgs(position, rawOpCode)); + } + + internal bool GetFpcrFlag(Fpcr flag) + { + return (Fpcr & (1 << (int)flag)) != 0; + } + + internal void SetFpsrFlag(Fpsr flag) + { + Fpsr |= 1 << (int)flag; + } + + internal RoundMode FPRoundingMode() + { + return (RoundMode)((Fpcr >> (int)State.Fpcr.RMode) & 3); + } + } +} diff --git a/ChocolArm64/State/ExecutionMode.cs b/ChocolArm64/State/ExecutionMode.cs new file mode 100644 index 00000000..4b8c17ce --- /dev/null +++ b/ChocolArm64/State/ExecutionMode.cs @@ -0,0 +1,8 @@ +namespace ChocolArm64.State +{ + enum ExecutionMode + { + AArch32, + AArch64 + } +} \ No newline at end of file diff --git a/ChocolArm64/State/FPCR.cs b/ChocolArm64/State/FPCR.cs deleted file mode 100644 index 8f47cf90..00000000 --- a/ChocolArm64/State/FPCR.cs +++ /dev/null @@ -1,11 +0,0 @@ -namespace ChocolArm64.State -{ - enum FPCR - { - UFE = 11, - RMode = 22, - FZ = 24, - DN = 25, - AHP = 26 - } -} diff --git a/ChocolArm64/State/FPExc.cs b/ChocolArm64/State/FPExc.cs deleted file mode 100644 index a665957d..00000000 --- a/ChocolArm64/State/FPExc.cs +++ /dev/null @@ -1,12 +0,0 @@ -namespace ChocolArm64.State -{ - enum FPExc - { - InvalidOp = 0, - DivideByZero = 1, - Overflow = 2, - Underflow = 3, - Inexact = 4, - InputDenorm = 7 - } -} diff --git a/ChocolArm64/State/FPSR.cs b/ChocolArm64/State/FPSR.cs deleted file mode 100644 index d71cde78..00000000 --- a/ChocolArm64/State/FPSR.cs +++ /dev/null @@ -1,8 +0,0 @@ -namespace ChocolArm64.State -{ - enum FPSR - { - UFC = 3, - QC = 27 - } -} diff --git a/ChocolArm64/State/FPType.cs b/ChocolArm64/State/FPType.cs deleted file mode 100644 index b00f5fee..00000000 --- a/ChocolArm64/State/FPType.cs +++ /dev/null @@ -1,11 +0,0 @@ -namespace ChocolArm64.State -{ - enum FPType - { - Nonzero, - Zero, - Infinity, - QNaN, - SNaN - } -} diff --git a/ChocolArm64/State/FpExc.cs b/ChocolArm64/State/FpExc.cs new file mode 100644 index 00000000..5cb7a402 --- /dev/null +++ b/ChocolArm64/State/FpExc.cs @@ -0,0 +1,12 @@ +namespace ChocolArm64.State +{ + enum FpExc + { + InvalidOp = 0, + DivideByZero = 1, + Overflow = 2, + Underflow = 3, + Inexact = 4, + InputDenorm = 7 + } +} diff --git a/ChocolArm64/State/FpType.cs b/ChocolArm64/State/FpType.cs new file mode 100644 index 00000000..fc279106 --- /dev/null +++ b/ChocolArm64/State/FpType.cs @@ -0,0 +1,11 @@ +namespace ChocolArm64.State +{ + enum FpType + { + Nonzero, + Zero, + Infinity, + QNaN, + SNaN + } +} diff --git a/ChocolArm64/State/Fpcr.cs b/ChocolArm64/State/Fpcr.cs new file mode 100644 index 00000000..908faee5 --- /dev/null +++ b/ChocolArm64/State/Fpcr.cs @@ -0,0 +1,11 @@ +namespace ChocolArm64.State +{ + enum Fpcr + { + Ufe = 11, + RMode = 22, + Fz = 24, + Dn = 25, + Ahp = 26 + } +} diff --git a/ChocolArm64/State/Fpsr.cs b/ChocolArm64/State/Fpsr.cs new file mode 100644 index 00000000..ba551eef --- /dev/null +++ b/ChocolArm64/State/Fpsr.cs @@ -0,0 +1,8 @@ +namespace ChocolArm64.State +{ + enum Fpsr + { + Ufc = 3, + Qc = 27 + } +} diff --git a/ChocolArm64/State/PState.cs b/ChocolArm64/State/PState.cs new file mode 100644 index 00000000..40636c87 --- /dev/null +++ b/ChocolArm64/State/PState.cs @@ -0,0 +1,23 @@ +using System; + +namespace ChocolArm64.State +{ + [Flags] + enum PState + { + VBit = 28, + CBit = 29, + ZBit = 30, + NBit = 31, + + V = 1 << VBit, + C = 1 << CBit, + Z = 1 << ZBit, + N = 1 << NBit, + + Nz = N | Z, + Cv = C | V, + + Nzcv = Nz | Cv + } +} diff --git a/ChocolArm64/State/Register.cs b/ChocolArm64/State/Register.cs new file mode 100644 index 00000000..ea29e7b6 --- /dev/null +++ b/ChocolArm64/State/Register.cs @@ -0,0 +1,142 @@ +using System; +using System.Reflection; + +namespace ChocolArm64.State +{ + struct Register + { + public int Index; + + public RegisterType Type; + + public Register(int index, RegisterType type) + { + Index = index; + Type = type; + } + + public override int GetHashCode() + { + return (ushort)Index | ((ushort)Type << 16); + } + + public override bool Equals(object obj) + { + return obj is Register reg && + reg.Index == Index && + reg.Type == Type; + } + + public FieldInfo GetField() + { + switch (Type) + { + case RegisterType.Flag: return GetFieldFlag(); + case RegisterType.Int: return GetFieldInt(); + case RegisterType.Vector: return GetFieldVector(); + } + + throw new InvalidOperationException(); + } + + private FieldInfo GetFieldFlag() + { + switch ((PState)Index) + { + case PState.VBit: return GetField(nameof(CpuThreadState.Overflow)); + case PState.CBit: return GetField(nameof(CpuThreadState.Carry)); + case PState.ZBit: return GetField(nameof(CpuThreadState.Zero)); + case PState.NBit: return GetField(nameof(CpuThreadState.Negative)); + } + + throw new InvalidOperationException(); + } + + private FieldInfo GetFieldInt() + { + switch (Index) + { + case 0: return GetField(nameof(CpuThreadState.X0)); + case 1: return GetField(nameof(CpuThreadState.X1)); + case 2: return GetField(nameof(CpuThreadState.X2)); + case 3: return GetField(nameof(CpuThreadState.X3)); + case 4: return GetField(nameof(CpuThreadState.X4)); + case 5: return GetField(nameof(CpuThreadState.X5)); + case 6: return GetField(nameof(CpuThreadState.X6)); + case 7: return GetField(nameof(CpuThreadState.X7)); + case 8: return GetField(nameof(CpuThreadState.X8)); + case 9: return GetField(nameof(CpuThreadState.X9)); + case 10: return GetField(nameof(CpuThreadState.X10)); + case 11: return GetField(nameof(CpuThreadState.X11)); + case 12: return GetField(nameof(CpuThreadState.X12)); + case 13: return GetField(nameof(CpuThreadState.X13)); + case 14: return GetField(nameof(CpuThreadState.X14)); + case 15: return GetField(nameof(CpuThreadState.X15)); + case 16: return GetField(nameof(CpuThreadState.X16)); + case 17: return GetField(nameof(CpuThreadState.X17)); + case 18: return GetField(nameof(CpuThreadState.X18)); + case 19: return GetField(nameof(CpuThreadState.X19)); + case 20: return GetField(nameof(CpuThreadState.X20)); + case 21: return GetField(nameof(CpuThreadState.X21)); + case 22: return GetField(nameof(CpuThreadState.X22)); + case 23: return GetField(nameof(CpuThreadState.X23)); + case 24: return GetField(nameof(CpuThreadState.X24)); + case 25: return GetField(nameof(CpuThreadState.X25)); + case 26: return GetField(nameof(CpuThreadState.X26)); + case 27: return GetField(nameof(CpuThreadState.X27)); + case 28: return GetField(nameof(CpuThreadState.X28)); + case 29: return GetField(nameof(CpuThreadState.X29)); + case 30: return GetField(nameof(CpuThreadState.X30)); + case 31: return GetField(nameof(CpuThreadState.X31)); + } + + throw new InvalidOperationException(); + } + + private FieldInfo GetFieldVector() + { + switch (Index) + { + case 0: return GetField(nameof(CpuThreadState.V0)); + case 1: return GetField(nameof(CpuThreadState.V1)); + case 2: return GetField(nameof(CpuThreadState.V2)); + case 3: return GetField(nameof(CpuThreadState.V3)); + case 4: return GetField(nameof(CpuThreadState.V4)); + case 5: return GetField(nameof(CpuThreadState.V5)); + case 6: return GetField(nameof(CpuThreadState.V6)); + case 7: return GetField(nameof(CpuThreadState.V7)); + case 8: return GetField(nameof(CpuThreadState.V8)); + case 9: return GetField(nameof(CpuThreadState.V9)); + case 10: return GetField(nameof(CpuThreadState.V10)); + case 11: return GetField(nameof(CpuThreadState.V11)); + case 12: return GetField(nameof(CpuThreadState.V12)); + case 13: return GetField(nameof(CpuThreadState.V13)); + case 14: return GetField(nameof(CpuThreadState.V14)); + case 15: return GetField(nameof(CpuThreadState.V15)); + case 16: return GetField(nameof(CpuThreadState.V16)); + case 17: return GetField(nameof(CpuThreadState.V17)); + case 18: return GetField(nameof(CpuThreadState.V18)); + case 19: return GetField(nameof(CpuThreadState.V19)); + case 20: return GetField(nameof(CpuThreadState.V20)); + case 21: return GetField(nameof(CpuThreadState.V21)); + case 22: return GetField(nameof(CpuThreadState.V22)); + case 23: return GetField(nameof(CpuThreadState.V23)); + case 24: return GetField(nameof(CpuThreadState.V24)); + case 25: return GetField(nameof(CpuThreadState.V25)); + case 26: return GetField(nameof(CpuThreadState.V26)); + case 27: return GetField(nameof(CpuThreadState.V27)); + case 28: return GetField(nameof(CpuThreadState.V28)); + case 29: return GetField(nameof(CpuThreadState.V29)); + case 30: return GetField(nameof(CpuThreadState.V30)); + case 31: return GetField(nameof(CpuThreadState.V31)); + } + + throw new InvalidOperationException(); + } + + private FieldInfo GetField(string name) + { + return typeof(CpuThreadState).GetField(name); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/State/RegisterSize.cs b/ChocolArm64/State/RegisterSize.cs new file mode 100644 index 00000000..7cc99599 --- /dev/null +++ b/ChocolArm64/State/RegisterSize.cs @@ -0,0 +1,10 @@ +namespace ChocolArm64.State +{ + enum RegisterSize + { + Int32, + Int64, + Simd64, + Simd128 + } +} \ No newline at end of file diff --git a/ChocolArm64/State/RegisterType.cs b/ChocolArm64/State/RegisterType.cs new file mode 100644 index 00000000..4476d044 --- /dev/null +++ b/ChocolArm64/State/RegisterType.cs @@ -0,0 +1,9 @@ +namespace ChocolArm64.State +{ + enum RegisterType + { + Flag, + Int, + Vector + } +} \ No newline at end of file diff --git a/ChocolArm64/State/RoundMode.cs b/ChocolArm64/State/RoundMode.cs new file mode 100644 index 00000000..b687cc8e --- /dev/null +++ b/ChocolArm64/State/RoundMode.cs @@ -0,0 +1,10 @@ +namespace ChocolArm64.State +{ + enum RoundMode + { + ToNearest = 0, + TowardsPlusInfinity = 1, + TowardsMinusInfinity = 2, + TowardsZero = 3 + } +} -- cgit v1.2.3