From c1bdf19061ec679aa3c69eda2a41337e3e809014 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Tue, 29 Jan 2019 13:06:11 -0300 Subject: Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table --- ChocolArm64/State/Register.cs | 1 + 1 file changed, 1 insertion(+) (limited to 'ChocolArm64/State/Register.cs') diff --git a/ChocolArm64/State/Register.cs b/ChocolArm64/State/Register.cs index 34588231..12c3f5c3 100644 --- a/ChocolArm64/State/Register.cs +++ b/ChocolArm64/State/Register.cs @@ -44,6 +44,7 @@ namespace ChocolArm64.State switch ((PState)Index) { case PState.TBit: return GetField(nameof(CpuThreadState.Thumb)); + case PState.EBit: return GetField(nameof(CpuThreadState.BigEndian)); case PState.VBit: return GetField(nameof(CpuThreadState.Overflow)); case PState.CBit: return GetField(nameof(CpuThreadState.Carry)); -- cgit v1.2.3