From e674b377104858d5068231dbe395e1038ba5d71d Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Tue, 23 Oct 2018 16:12:45 +0200
Subject: Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to
 half conv. (full FP emu.). Add 4 FP Tests. (#468)

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
---
 ChocolArm64/State/FPSR.cs | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 ChocolArm64/State/FPSR.cs

(limited to 'ChocolArm64/State/FPSR.cs')

diff --git a/ChocolArm64/State/FPSR.cs b/ChocolArm64/State/FPSR.cs
new file mode 100644
index 00000000..d71cde78
--- /dev/null
+++ b/ChocolArm64/State/FPSR.cs
@@ -0,0 +1,8 @@
+namespace ChocolArm64.State
+{
+    enum FPSR
+    {
+        UFC = 3,
+        QC  = 27
+    }
+}
-- 
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