From 36b9ab0e48b6893c057a954e1ef3181b452add1c Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 24 Jan 2019 23:59:53 -0200 Subject: Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check --- ChocolArm64/State/CpuThreadState.cs | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'ChocolArm64/State/CpuThreadState.cs') diff --git a/ChocolArm64/State/CpuThreadState.cs b/ChocolArm64/State/CpuThreadState.cs index a4ee5d07..6c00bf48 100644 --- a/ChocolArm64/State/CpuThreadState.cs +++ b/ChocolArm64/State/CpuThreadState.cs @@ -8,25 +8,13 @@ namespace ChocolArm64.State { public class CpuThreadState { - internal const int LrIndex = 30; - internal const int ZrIndex = 31; - internal const int ErgSizeLog2 = 4; internal const int DczSizeLog2 = 4; private const int MinInstForCheck = 4000000; - internal ExecutionMode ExecutionMode; - - //AArch32 state. - public uint R0, R1, R2, R3, - R4, R5, R6, R7, - R8, R9, R10, R11, - R12, R13, R14, R15; - public bool Thumb; - //AArch64 state. public ulong X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, @@ -42,6 +30,10 @@ namespace ChocolArm64.State public bool Zero; public bool Negative; + public bool IsAarch32; + + public int ElrHyp; + public bool Running { get; set; } public int Core { get; set; } @@ -146,6 +138,18 @@ namespace ChocolArm64.State Undefined?.Invoke(this, new InstUndefinedEventArgs(position, rawOpCode)); } + internal ExecutionMode GetExecutionMode() + { + if (!IsAarch32) + { + return ExecutionMode.Aarch64; + } + else + { + return Thumb ? ExecutionMode.Aarch32Thumb : ExecutionMode.Aarch32Arm; + } + } + internal bool GetFpcrFlag(Fpcr flag) { return (Fpcr & (1 << (int)flag)) != 0; -- cgit v1.2.3