From e674b377104858d5068231dbe395e1038ba5d71d Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Tue, 23 Oct 2018 16:12:45 +0200
Subject: Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to
 half conv. (full FP emu.). Add 4 FP Tests. (#468)

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
---
 ChocolArm64/State/AThreadState.cs | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

(limited to 'ChocolArm64/State/AThreadState.cs')

diff --git a/ChocolArm64/State/AThreadState.cs b/ChocolArm64/State/AThreadState.cs
index e4953b02..fbfac5bc 100644
--- a/ChocolArm64/State/AThreadState.cs
+++ b/ChocolArm64/State/AThreadState.cs
@@ -145,5 +145,20 @@ namespace ChocolArm64.State
         {
             Undefined?.Invoke(this, new AInstUndefinedEventArgs(Position, RawOpCode));
         }
+
+        internal bool GetFpcrFlag(FPCR Flag)
+        {
+            return (Fpcr & (1 << (int)Flag)) != 0;
+        }
+
+        internal void SetFpsrFlag(FPSR Flag)
+        {
+            Fpsr |= 1 << (int)Flag;
+        }
+
+        internal ARoundMode FPRoundingMode()
+        {
+            return (ARoundMode)((Fpcr >> (int)FPCR.RMode) & 3);
+        }
     }
-}
\ No newline at end of file
+}
-- 
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