From 10c74182babaf8cf6bedaeffd64c3109df4ea816 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Sun, 30 Jun 2019 01:02:48 +0200 Subject: Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709) * Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests. --- ChocolArm64/Instructions/InstEmitSimdMove.cs | 38 +++++++++------------------- 1 file changed, 12 insertions(+), 26 deletions(-) (limited to 'ChocolArm64/Instructions/InstEmitSimdMove.cs') diff --git a/ChocolArm64/Instructions/InstEmitSimdMove.cs b/ChocolArm64/Instructions/InstEmitSimdMove.cs index 841dcfe7..647a2238 100644 --- a/ChocolArm64/Instructions/InstEmitSimdMove.cs +++ b/ChocolArm64/Instructions/InstEmitSimdMove.cs @@ -220,45 +220,37 @@ namespace ChocolArm64.Instructions public static void Fmov_Ftoi(ILEmitterCtx context) { - OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp; - - EmitVectorExtractZx(context, op.Rn, 0, 3); + OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; - EmitIntZeroUpperIfNeeded(context); + EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2); context.EmitStintzr(op.Rd); } public static void Fmov_Ftoi1(ILEmitterCtx context) { - OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp; + OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; EmitVectorExtractZx(context, op.Rn, 1, 3); - EmitIntZeroUpperIfNeeded(context); - context.EmitStintzr(op.Rd); } public static void Fmov_Itof(ILEmitterCtx context) { - OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp; + OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; context.EmitLdintzr(op.Rn); - EmitIntZeroUpperIfNeeded(context); - - EmitScalarSet(context, op.Rd, 3); + EmitScalarSet(context, op.Rd, op.Size + 2); } public static void Fmov_Itof1(ILEmitterCtx context) { - OpCodeSimdCvt64 op = (OpCodeSimdCvt64)context.CurrOp; + OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; context.EmitLdintzr(op.Rn); - EmitIntZeroUpperIfNeeded(context); - EmitVectorInsert(context, op.Rd, 1, 3); } @@ -280,7 +272,7 @@ namespace ChocolArm64.Instructions EmitScalarSet(context, op.Rd, op.Size + 2); } - public static void Fmov_V(ILEmitterCtx context) + public static void Fmov_Vi(ILEmitterCtx context) { OpCodeSimdImm64 op = (OpCodeSimdImm64)context.CurrOp; @@ -347,7 +339,11 @@ namespace ChocolArm64.Instructions EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size); - EmitIntZeroUpperIfNeeded(context); + if (op.RegisterSize == RegisterSize.Simd64) + { + context.Emit(OpCodes.Conv_U4); + context.Emit(OpCodes.Conv_U8); + } context.EmitStintzr(op.Rd); } @@ -544,16 +540,6 @@ namespace ChocolArm64.Instructions EmitVectorZip(context, part: 1); } - private static void EmitIntZeroUpperIfNeeded(ILEmitterCtx context) - { - if (context.CurrOp.RegisterSize == RegisterSize.Int32 || - context.CurrOp.RegisterSize == RegisterSize.Simd64) - { - context.Emit(OpCodes.Conv_U4); - context.Emit(OpCodes.Conv_U8); - } - } - private static void EmitMoviMvni(ILEmitterCtx context, bool not) { OpCodeSimdImm64 op = (OpCodeSimdImm64)context.CurrOp; -- cgit v1.2.3